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IS43DR16160A-37CBL Datasheet(PDF) 9 Page - Integrated Silicon Solution, Inc

Part # IS43DR16160A-37CBL
Description  32Mx8, 16Mx16 DDR2 DRAM
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS43DR16160A-37CBL Datasheet(HTML) 9 Page - Integrated Silicon Solution, Inc

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Integrated Silicon Solution, Inc. — www.issi.com
9
Rev. D
08/16/2012
IS43/46DR83200A, IS43/46DR16160A
Input DC logic level
Symbol
Parameter
Min.
Max.
Units
Notes
VIH(dc)
dc input logic HIGH
VREF + 0.125
VDDQ + 0.3
V
VIL(dc)
dc input logic LOW
- 0.3
VREF - 0.125
V
Input AC logic level
Symbol Parameter
DDR2-400, DDR2-533
DDR2-667, DDR2-800
Units Notes
Min.
Max.
Min.
Max
VIH (ac) ac input logic HIGH
VREF + 0.250
VDDQ + Vpeak
VREF + 0.200
VDDQ + Vpeak
V
1
VIL (ac) ac input logic LOW
VSSQ - Vpeak
VREF - 0.250
VSSQ - Vpeak
VREF - 0.200
V
1
AC Input Test Conditions
Symbol
Condition
Value
Units
Notes
VREF
Input reference voltage
0.5 x VDDQ
V
1
VSWING(MAX) Input signal maximum peak to peak swing
1.0
V
1
SLEW
Input signal minimum slew rate
1.0
V/ns
2, 3
Notes:
1. Refer to Overshoot/undershoot specifications for Vpeak value: maximum peak amplitude allowed for overshoot and undershoot.
Notes:
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to
VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the
negative transitions.
AC input test signal waveform
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc) max
VIL(ac) max
VSS
VSWING(MAX)
DTR
DTF
VREF - VIL(ac) max
DTF
Falling Slew =
Rising Slew =
VIH(ac) min - VREF
DTR


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