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HMT351U7CFR8A-PB Datasheet(PDF) 7 Page - Hynix Semiconductor

Part # HMT351U7CFR8A-PB
Description  DDR3L SDRAM Unbuffered DIMMs Based on 2Gb C-Die
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

HMT351U7CFR8A-PB Datasheet(HTML) 7 Page - Hynix Semiconductor

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Rev. 1.1 / Jul. 2013
7
DQS0–DQS8
DQS0–DQS8
SSTL
Differential
crossing
Data strobe for input and output data.
SA0–SA2
—
These signals are tied at the system planar to either VSS or VDDSPD to con-
figure the serial SPD EEPROM address range.
SDA
—
This bidirectional pin is used to transfer data into or out of the SPD
EEPROM. An external resistor may be connected from the SDA bus line to
VDDSPD to act as a pullup on the system board.
SCL
—
This signal is used to clock data into and out of the SPD EEPROM. An
external resistor may be connected from the SCL bus time to VDDSPD to act
as a pullup on the system board.
VDDSPD
Supply
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ
power plane. EEPROM supply is operable from 3.0V to 3.6V.
Symbol
Type
Polarity
Function


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