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HMT351S6EFR8C-RD Datasheet(PDF) 6 Page - Hynix Semiconductor |
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HMT351S6EFR8C-RD Datasheet(HTML) 6 Page - Hynix Semiconductor |
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6 / 50 page  Rev.1.3 /Sep. 2013 6 Input/Output Functional Descriptions Symbol Type Polarity Function CK0/CK0 CK1/CK1 IN Cross Point The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. CKE[1:0] IN Active High Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. S[1:0] IN Active Low Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1. ODT[1:0] IN Active High Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3 SDRAM mode register. RAS, CAS, WE IN Active Low When sampled at the cross point of the rising edge of CK, signals CAS, RAS, and WE define the operation to be executed by the SDRAM. VREFDQ VREFCA Supply Reference voltage for SSTL15 inputs. BA[2:0] IN — Selects which SDRAM internal bank of eight is activated. A[9:0], A10/AP, A11, A12/BC A[15:13] IN — During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read of Write com- mand cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pre- charged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. A12(BC) is samples during READ and WRITE com- mands to determine if burst chop (on-the-fly) will be performed (HIGH, no burst chop: LOW, burst chopped). DQ[63:0] I/O — Data Input/Output pins. DM[7:0] IN Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. VDD, VDDSPD VSS Supply Power supplies for core, I/O, Serial Presence Detect, and ground for the module. DQS[7:0], DQS[7:0] I/O Cross Point The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR3 SDRAMs and is sent at the lead- ing edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. SA[1:0] IN — These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. |
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