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BQ34Z950DBTR Datasheet(PDF) 11 Page - Texas Instruments |
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BQ34Z950DBTR Datasheet(HTML) 11 Page - Texas Instruments |
11 / 28 page SMBC SMBD SMBC SMBD SMBC SMBD S tSU(STA) S P tBUF tSU(STO) tR tF SMBC SMBD tTIMEOUT tHIGH tLOW tF tR tHD(DAT) tSU(DAT) tHD(STA) Start and Stop condition Wait and Hold condition Timeout condition Repeated Start condition bq34z950 www.ti.com SLUSBF0A – APRIL 2013 – REVISED MAY 2013 SMBus TIMING CHARACTERISTICS (continued) TA = –40°C to 85°C Typical Values at TA = 25°C and VREG25 = 2.5 V (Unless Otherwise Noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t(SU:DAT) Data setup time (see Figure 1) 250 ns t(TIMEOUT) Error signal/detect (see Figure 1) See (1) 25 35 µs t(LOW) Clock low period (see Figure 1) 4.7 µs t(HIGH) Clock high period (see Figure 1) See (2) 4 50 µs t(LOW:SEXT) Cumulative clock low slave extend time See (3) 25 ms Cumulative clock low master extend time t(LOW:MEXT) See (4) 10 ms (see Figure 1) tf Clock/data fall time See (5) 300 ns tr Clock/data rise time See (6) 1000 ns (1) The bq34z950 times out when any clock low exceeds t(TIMEOUT). (2) t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving bq34z950 that is in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0). (3) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop. (4) t(LOW:MEXT) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop. (5) Rise time tr = VILMAX – 0.15) to (VIHMIN + 0.15) (6) Fall time tf = 0.9VDD to (VILMAX – 0.15) A. SCLKACK is the acknowledge-related clock pulse generated by the master. Figure 1. SMBus Timing Diagram Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: bq34z950 |
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