14-Bit, 20/40/65/80 MSPS,

1.8 V Analog-to-Digital Converter

AD9649

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother

rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

©2009 Analog Devices, Inc. All rights reserved.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother

rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

©2009 Analog Devices, Inc. All rights reserved.

FEATURES

1.8 V analog supply operation

1.8 V to 3.3 V output supply

SNR

74.3 dBFS at 9.7 MHz input

71.5 dBFS at 200 MHz input

SFDR

93 dBc at 9.7 MHz input

80 dBc at 200 MHz input

Low power

45 mW at 20 MSPS

87 mW at 80 MSPS

Differential input with 700 MHz bandwidth

On-chip voltage reference and sample-and-hold circuit

2 V p-p differential analog input

DNL = ±0.35 LSB

Serial port control options

Offset binary, gray code, or twos complement data format

Integer 1, 2, or 4 input clock divider

Built-in selectable digital test pattern generation

Energy-saving power-down modes

Data clock out (DCO) with programmable clock and data

alignment

APPLICATIONS

Communications

Diversity radio systems

Multimode digital receivers

GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA

Smart antenna systems

Battery-powered instruments

Handheld scope meters

Portable medical imaging

Ultrasound

Radar/LIDAR

FUNCTIONAL BLOCK DIAGRAM

SPI

MODE

CONTROLS

DIVIDE BY

1, 2, 4

REF

SELECT

VIN+

VIN–

VREF

SENSE

CLK+ CLK–

AVDD

GND

SDIO SCLK

CSB

PDWN

AD9649

DFS

MODE

D0 (LSB)

DCO

D13 (MSB)

OR

ADC

CORE

PROGRAMMING DATA

RBIAS

VCM

DRVDD

Figure 1.

PRODUCT HIGHLIGHTS

1.

The AD9649 operates from a single 1.8 V analog power

supply and features a separate digital output driver supply

to accommodate 1.8 V to 3.3 V logic families.

2.

The patented sample-and-hold circuit maintains excellent

performance for input frequencies up to 200 MHz and is

designed for low cost, low power, and ease of use.

3.

A standard serial port interface (SPI) supports various

product features and functions, such as data output format-

ting, internal clock divider, power-down, DCO, data output

(D13 to D0) timing and offset adjustments, and voltage

reference modes.

4.

The AD9649 is packaged in a 32-lead RoHS-compliant LFCSP

that is pin compatible with the AD9629 12-bit ADC and

the AD9609 10-bit ADC, enabling a simple migration path

between 10-bit and 14-bit converters sampling from 20 MSPS

to 80 MSPS.