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H5PS1G83JFR Datasheet(PDF) 58 Page - Hynix Semiconductor

Part # H5PS1G83JFR
Description  1Gb DDR2 SDRAM
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5PS1G83JFR Datasheet(HTML) 58 Page - Hynix Semiconductor

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Rev. 1.7 / Apr. 2012
58
Release
H5PS1G83JFR Series
24. These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1,
etc.) transition edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of
clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that
latches the command/address. That is, these parameters should be met whether clock jitter is present or not.
25. These parameters are measured from a data strobe signal ((L/U/R)DQS/DQS) crossing to its respective clock
signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc),
etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is
present or not.
26.
These parameters are measured from a data signal ((L/U) DM, (L/U) DQ0, (L/U) DQ1, etc.) transition
edge to its respective data strobe signal ((L/U/R)DQS/DQS) crossing.
27. For these parameters, the DDR2 SDRAM device is characterized and verified to support
tnPARAM = RU{tPARAM / tCK(avg)}, which is in clock cycles, assuming all input clock jitter specifications
are satisfied.
For example, the device will support tnRP = RU {tRP / tCK(avg)}, which is in clock cycles, if all input clock
jitterspecifications are met. This means: For DDR2-1066 7-7-7, of which tRP = 13.125ns, the device will
support tnRP =RU{tRP / tCK(avg)} = 7, i.e. as long as the input clock jitter specifications are met, Pre-
charge command at Tm and Active command at Tm+7 is valid even if (Tm+7 - Tm) is less than 13.127ns
due to input clock jitter.
28. Specific Note 28 tDAL
nCK = WR nCK + tnRP nCK = WR + RUtRP ps / tCK(avg) ps, where WR is the
value programmed in the mode register set and RU stands for round up.
Example: For DDR2-1066 7-7-7 at tCK(avg) = 1.875 ns with WR programmed to 8 nCK,
tDAL = 8 + RU
13.125 ns / 1.875 ns nCK = 8 + 7 nCK = 15 nCK
29.New units, ‘tCK(avg)’ and ‘nCK’, are introduced in DDR2-1066.
Unit ‘tCK(avg)’ represents the actual tCK(avg) of the input clock under operation.
Unit ‘nCK’ represents one clock cycle of the input clock, counting the actual clock edges.
ex) tXP = 3 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+3,
even if (Tm+3 - Tm) is 3 x tCK(avg) + tERR(3per),min.
30.
Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as
'input clock jitter spec parameters' and these parameters apply to DDR2-1066. The jitter specified is a ran-
dom jitter meeting a Gaussian distribution.


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