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H5PS5182GFRS6C Datasheet(PDF) 29 Page - Hynix Semiconductor

Part # H5PS5182GFRS6C
Description  512Mb DDR2 SDRAM
Download  64 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5PS5182GFRS6C Datasheet(HTML) 29 Page - Hynix Semiconductor

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Rev.1.7 / Feb. 2013
29
H5PS5162GFR series
1) For all input signals the total tDS(setup time) and tDH(hold time) required is calculated by adding the datasheet value to the derating
value listed in Table x.
Setup(tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing
of Vih(ac)min. Setup(tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the
first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded ‘ VREF(dc) to ac region’,
use nominal slew rate for derating value(see Fig a.) If the actual signal is later than the nominal slew rate line anywhere between shaded
‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value(see Fig b.)
Hold(tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc) max and the first crossing
of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc) min and the
first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc)
region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see Fig c.) If the
actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line
to the actual signal from the dc level to VREF(dc) level is used for derating value(see Fig d.)
Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the time
of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
tDS
tDH
tDS
tDH
tD S
tDH
tD S
tDH
tD S
tD H
tDS
tD H
tDS
tD H
tDS
tDH
tDS
tDH
2 .0
1 8 8
1 88
1 6 7
14 6
1 2 5
6 3
--
--
--
-
-
--
--
1 .5
1 46
167
1 2 5
12 5
8 3
4 2
8 1
4 3
-
-
-
-
-
-
-
-
-
-
1 .0
6 3
1 25
4 2
83
0
0
- 2
1
-7
-1 3
--
-
-
--
--
0 .9
-
-
3 1
69
- 11
-1 4
- 13
-1 3
- 18
-2 7
- 29
-4 5
-
-
-
-
-
-
0 .8
-
-
-
-
- 25
-3 1
- 27
-3 0
- 32
-4 4
- 43
-6 2
-6 0
-8 6
-
-
-
-
0 .7
-
-
-
-
-
-
- 45
-5 3
- 50
-6 7
- 61
-8 5
-7 8
-1 09
- 10 8
-1 52
-
-
0 .6
-
-
-
-
-
-
-
-
-74
-96
- 85
-11 4 - 10 2
-138
- 13 2
-181
-1 8 3 - 248
0 .5
-
--
--
---
--
- 12 8
-1 5 6 - 14 5
-1 80
- 17 5
-2 23
-2 2 6 - 2 88
0 .4
-
--
--
---
--
--
- 21 0
-2 43
- 24 0
-2 86
-2 9 1 - 3 51
tD S, t DH De ra ting V a lues fo r D DR2 -4 0 0, D DR2 -5 3 3( ALL un it s in ' ps ', Not e 1 a pplies to e nt ire Ta ble )
0.8 V/ns
0.7 V/ns
0 .6 V /ns
0.5 V/ns
2.0 V /ns
1.5 V /n s
1.0 V /n s
0.9 V/n s
0.4 V/ns
DQ
Sle w
rat e
V/ns
DQ S, S ingle -e nde d S lew R at e


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