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H5PS5182GFRS6C Datasheet(PDF) 39 Page - Hynix Semiconductor

Part # H5PS5182GFRS6C
Description  512Mb DDR2 SDRAM
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5PS5182GFRS6C Datasheet(HTML) 39 Page - Hynix Semiconductor

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Rev.1.7 / Feb. 2013
39
H5PS5162GFR series
22. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising sig-
nal and VIL(ac) for a falling signal applied to the device under test.
23. Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising sig-
nal and VIH(dc) for a falling signal applied to the device under test.
24. tWTR is at least two clocks (2 x tCK or 2 x nCK) independent of operation frequency.
25. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the
input signal crossing at the VIH (ac) level to the single-ended data strobe crossing VIH/L (dc) at the start
of its transition for a rising signal, and from the input signal crossing at the VIL (ac) level to the single-
ended data strobe crossing VIH/L (dc) at the start of its transition for a falling signal applied to the device
under test. The DQS signal must be monotonic between Vil(dc)max and Vih (dc) min.
26. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the
input signal crossing at the VIH(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of
its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the single-ended
data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under
test. The DQS signal must be monotonic between Vil(dc)max and Vih (dc) min.
27. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE
must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus,
after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK
+ tIH.
28. If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data
before a valid READ can be executed.
29. These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0,
A0, A1, etc.) transition edge to its respective clock signal (CK/CK) crossing. The spec values are not
affected by the amount of clock jitter applied (i.e. tJIT (per), tJIT (cc), etc.), as the setup and hold are rel-
ative to the clock signal crossing that latches the command/address. That is, these parameters should be
met whether clock jitter is present or not.
30. These parameters are measured from a data strobe signal ((L/U/R)DQS/DQS) crossing to its respective
clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
tJIT (per), tJIT (cc), etc.), as these are relative to the clock signal crossing. That is, these parameters
should be met whether clock jitter is present or not.
31. These parameters are measured from a data signal ((L/U) DM, (L/U) DQ0, (L/U) DQ1, etc.) transition
edge to its respective data strobe signal ((L/U/R)DQS/DQS) crossing.
32. For these parameters, the DDR2 SDRAM device is characterized and verified to support


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