H5PS1G63JFRS6C datasheet(21/62 Pages) HYNIX

Part No.	H5PS1G63JFRS6C

Description	1Gb DDR2 SDRAM

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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21 / 62 page

Rev. 1.7 / Nov. 2011

21

Release

H5PS1G63JFR Series

Timing Parameters by Speed Grade (DDR2-400 and DDR2-533)

Parameter

Symbol

DDR2-400

DDR2-533

Unit

Note

min

max

min

max

DQ output access time from CK/CK

tAC

-600

+600

-500

+500

ps

DQS output access time from CK/CK

tDQSCK

-500

+500

-450

+450

ps

CK HIGH pulse width

tCH

0.45

0.55

0.45

0.55

tCK

CK LOW pulse width

tCL

0.45

0.55

0.45

0.55

tCK

CK half period

tHP

min(tCL,

tCH)

-

min(tCL,

tCH)

-

ps

11,12

Clock cycle time, CL=x

tCK

5000

8000

3750

8000

ps

15

DQ and DM input setup time(differential strobe)

tDS(base)

150

-

100

-

ps

6,7,8,20

,28

DQ and DM input hold time(differential strobe)

tDH(base)

275

-

225

-

ps

6,7,8,21

,28

DQ and DM input setup time(single ended strobe)

tDS(base)

25

--25

-

ps

6,7,8,25

DQ and DM input hold time(single ended strobe)

tDH(base)

25

--25

-

ps

6,7,8,26

Control & Address input pulse width for each

input

tIPW

0.6

-

0.6

-

tCK

DQ and DM input pulse width for each input

tDIPW

0.35

-

0.35

-

tCK

Data-out high-impedance time from CK/CK

tHZ

-

tAC max

-

tAC max

ps

18

DQS low-impedance time from CK/CK

tLZ

(DQS)

tAC min

tAC max

tAC min

tAC max

ps

18

DQ low-impedance time from CK/CK

tLZ

(DQ)

2*tAC min

tAC max

2*tAC min

tAC max

ps

18

DQS-DQ skew for DQS and associated DQ

signals

tDQSQ

-

350

-

300

ps

13

DQ hold skew factor

tQHS

-

450

-

400

ps

12

DQ/DQS output hold time from DQS

tQH

tHP - tQHS

-

tHP - tQHS

-

ps

Write command to first DQS latching transition

tDQSS

WL - 0.25

WL + 0.25

WL - 0.25

WL + 0.25

tCK

DQS input HIGH pulse width

tDQSH

0.35

-

0.35

-

tCK

DQS input LOW pulse width

tDQSL

0.35

-

0.35

-

tCK

DQS falling edge to CK setup time

tDSS

0.2

-

0.2

-

tCK

DQS falling edge hold time from CK

tDSH

0.2

-

0.2

-

tCK

Mode register set command cycle time

tMRD

2

-

2

-

tCK

Write preamble

tWPRE

0.35

-

0.35

-

tCK

Write postamble

tWPST

0.4

0.6

0.4

0.6

tCK

10

Address and control input setup time

tIS

350

-

250

-

ps

5,7,9,23

Address and control input hold time

tIH

475

-

375

-

ps

5,7,9,23

Read preamble

tRPRE

0.9

1.1

0.9

1.1

tCK

19

Read postamble

tRPST

0.4

0.6

0.4

0.6

tCK

19

Active to active command period for 1KB

page size products (x4, x8)

tRRD

7.5

-7.5

-

ns

4

Active to active command period for 2KB

page size products (x16)

tRRD

10

-10

-

ns

4

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H5PS1G63JFRS6C Datasheet(PDF) 21 Page - Hynix Semiconductor

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