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H5PS1G63JFRS6C Datasheet(PDF) 39 Page - Hynix Semiconductor

Part # H5PS1G63JFRS6C
Description  1Gb DDR2 SDRAM
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5PS1G63JFRS6C Datasheet(HTML) 39 Page - Hynix Semiconductor

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Rev. 1.7 / Nov 2011
39
Release
H5PS1G63JFR Series
32. For these parameters, the DDR2 SDRAM device is characterized and verified to support
tnPARAM = RU {tPARAM / tCK (avg)}, which is in clock cycles, assuming all input clock jitter specifications
are satisfied.
For example, the device will support tnRP = RU {tRP / tCK (avg)}, which is in clock cycles, if all input clock
jitter specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15ns, the device will support
tnRP =RU {tRP / tCK (avg)} = 5, i.e. as long as the input clock jitter specifications are met, Precharge
command at Tm and Active command at Tm+5 is valid even if (Tm+5 - Tm) is less than 15ns due to input
clock jitter.
33. tDAL [nCK] = WR [nCK] + tnRP [nCK] = WR + RU {tRP [ps] / tCK (avg) [ps]}, where WR is the value
programmed in the mode register set.
34. New units, ‘tCK (avg)’ and ‘nCK’, are introduced in DDR2-667 and DDR2-800.
Unit ‘tCK (avg)’ represents the actual tCK (avg) of the input clock under operation.
Unit ‘nCK’, represents one clock cycle of the input clock, counting the actual clock edges.
Note that in DDR2-400 and DDR2-533, ‘tCK’, is used for both concepts.
ex) tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered
at Tm+2, even if (Tm+2 - Tm) is 2 x tCK (avg) + tERR(2per),min.
35. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as
'input clock jitter spec parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter
specified is a random jitter meeting a Gaussian distribution.
Parameter
Symbol
DDR2-667
DDR2-800
Units
Notes
min
max
min
max
Clock period jitter
tJIT (per)
-125
125
-100
100
ps
35
Clock period jitter during DLL locking period
tJIT (per, lck)
-100
100
-80
80
ps
35
Cycle to cycle clock period jitter
tJIT (cc)
-250
250
-200
200
ps
35
Cycle to cycle clock period jitter during DLL
locking period
tJIT (cc, lck)
-200
200
-160
160
ps
35
Cumulative error across 2 cycles
tERR(2per)
-175
175
-150
150
ps
35
Cumulative error across 3 cycles
tERR(3per)
-225
225
-175
175
ps
35
Cumulative error across 4 cycles
tERR(4per)
-250
250
-200
200
ps
35
Cumulative error across 5 cycles
tERR(5per)
-250
250
-200
200
ps
35
Cumulative error across n cycles,
n=6...10, inclusive
tERR(6~10per)
-350
350
-300
300
ps
35
Cumulative error across n cycles,
n=11...50, inclusive
tERR(11~50per)
-450
450
-450
450
ps
35
Duty cycle jitter
tJIT (duty)
-125
125
-100
100
ps
35


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