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H5PS1G63JFRS6C Datasheet(PDF) 46 Page - Hynix Semiconductor

Part # H5PS1G63JFRS6C
Description  1Gb DDR2 SDRAM
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5PS1G63JFRS6C Datasheet(HTML) 46 Page - Hynix Semiconductor

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Rev. 1.7 / Nov 2011
46
Release
H5PS1G63JFR Series
Timing Parameters by Speed Grade
(Refer to notes for information related to this table at the following pages of this table)
Parameter
Symbol
DDR2-1066
Unit
Note
min
max
DQ output access time from CK/CK
tAC
-350
+350
ps
35
DQS output access time from CK/CK
tDQSCK
-325
+325
ps
35
CK high-level width
tCH
0.48
0.52
tCK
30, 31
CK low-level width
tCL
0.48
0.52
tCK
30, 31
CK half period
tHP
min
(tCL,tCH)
-
ps
32
Clock cycle time, CL=x
tCK
1875
7500
ps
30, 31
DQ and DM input setup time
(differential strobe)
tDS
(base)
0
-
ps
6,7,8,
17, 23,
26
DQ and DM input hold time
(differential strobe)
tDH
(base)
75
-
ps
6,7,8,
16, 23,
26
Control & Address input pulse width for each input
tIPW
0.6
-
tCK(avg)
DQ and DM input pulse width for each input
tDIPW
0.35
-
tCK(avg)
Data-out high-impedance time from CK/CK
tHZ
-
tAC max
ps
15, 35
DQS low-impedance time from CK/CK
tLZ(DQS)
tAC min
tAC max
ps
15, 35
DQ low-impedance time from CK/CK
tLZ(DQ)
2*tAC min
tAC max
ps
15, 35
DQS-DQ skew for DQS and associated DQ signals
tDQSQ
-
175
ps
11
DQ hold skew factor
tQHS
-
250
ps
33
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
-
ps
34
First DQS latching transition to associated clock edge
tDQSS
-0.25
+ 0.25
tCK(avg)
25
DQS input high pulse width
tDQSH
0.35
-
tCK(avg)
DQS input low pulse width
tDQSL
0.35
-
tCK(avg)
DQS falling edge to CK setup time
tDSS
0.2
-
tCK(avg)
25
DQS falling edge hold time from CK
tDSH
0.2
-
tCK(avg)
25
Mode register set command cycle time
tMRD
2
-
tCK
Write postamble
tWPST
0.4
0.6
tCK(avg)
10
Write preamble
tWPRE
0.35
-
tCK(avg)
Address and control input setup time
tIS(base)
125
-
ps
5,7,9,
19, 24
Address and control input hold time
tIH(base)
200
-
ps
5,7,9,
20, 24


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