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H5PS1G63JFRS6C Datasheet(PDF) 59 Page - Hynix Semiconductor

Part # H5PS1G63JFRS6C
Description  1Gb DDR2 SDRAM
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5PS1G63JFRS6C Datasheet(HTML) 59 Page - Hynix Semiconductor

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Rev. 1.7 / Nov 2011
59
Release
H5PS1G63JFR Series
31. These parameters are specified per their average values, however it is understood that the following
relationship between the average timing and the absolute instantaneous timing holds at all times. (Min and
max of SPEC values are to be used for calculations in the table below.
Example: For DDR2-1066, tCH(abs),min = ( 0.48 x 1875 ps ) - 75 ps = 825 ps
32. tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input
specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH.
The value to be used for tQH calculation is determined by the following equation;
tHP = Min ( tCH(abs), tCL(abs) ),
where,
tCH(abs) is the minimum of the actual instantaneous clock HIGH time;
tCL(abs) is the minimum of the actual instantaneous clock LOW time;
Parameter
Symbol
DDR2-1066
Units
Notes
min
max
Clock period jitter
tJIT(per)
-90
90
ps
30
Clock period jitter during DLL locking period
tJIT(per,lck)
-80
80
ps
30
Cycle to cycle clock period jitter
tJIT(cc)
-180
180
ps
30
Cycle to cycle clock period jitter during DLL lock-
ing period
tJIT(cc,lck)
-160
160
ps
30
Cumulative error across 2 cycles
tERR(2per)
-132
132
ps
30
Cumulative error across 3 cycles
tERR(3per)
-157
157
ps
30
Cumulative error across 4 cycles
tERR(4per)
-175
175
ps
30
Cumulative error across 5 cycles
tERR(5per)
-188
188
ps
30
Cumulative error across n cycles,
n=6...10, inclusive
tERR(6~10per)
-250
250
ps
30
Cumulative error across n cycles,
n=11...50, inclusive
tERR(11~50per)
-425
425
ps
30
Duty cycle jitter
tJIT(duty)
-75
75
ps
30
Parameter
Symbol
min
max
Units
Absolute clock period
tCK(abs)
tCK(avg),min+tJIT(per),min
tCK(avg),max+tJIT(per),max
ps
Absolute clock HIGH pulse width
tCH(abs)
tCH(avg),min x tCK(avg),min +
tJIT(duty),min
tCH(avg),max x tCK(avg),max +
tJIT(duty),max
ps
Absolute clock LOW pulse width
tCL(abs)
tCL(avg),min x tCK(avg),min +
tJIT(duty),min
tCL(avg),max x tCK(avg),max +
tJIT(duty),max
ps


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