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H5PS5162GFRS6C Datasheet(PDF) 13 Page - Hynix Semiconductor

Part # H5PS5162GFRS6C
Description  512Mb DDR2 SDRAM
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

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Rev.1.7 / Feb. 2013
13
H5PS5162GFR series
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
3.2.2 Input AC Logic Level
3.2.3 AC Input Test Conditions
Note:
1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device
under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising
edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions
and VIH(ac) to VIL(ac) on the negative transitions.
Symbol
Parameter
Min.
Max.
Units
Notes
VIH(dc)
dc input logic high
VREF + 0.125
VDDQ + 0.3
V
VIL(dc)
dc input logic low
- 0.3
VREF - 0.125
V
Symbol
Parameter
DDR2 400,533
DDR2 667,800
Units
Notes
Min.
Max.
Min.
Max.
VIH (ac)
ac input logic high
VREF +
0.250
-
VREF +
0.200
-V
VIL (ac)
ac input logic low
-
VREF - 0.250
-
VREF - 0.200
V
Symbol
Condition
Value
Units
Notes
VREF
Input reference voltage
0.5 * VDDQ
V1
VSWING(MAX)
Input signal maximum peak to peak swing
1.0
V
1
SLEW
Input signal minimum slew rate
1.0
V/ns
2, 3
VDDQ
VIH(ac) min
VREF
VSWING(MAX)
delta TR
delta TF
VIH(dc) min
VIL(dc) max
VIL(ac) max
VSS
Rising Slew =
delta TR
VIH(ac) min - VREF
VREF - VIL(ac) max
delta TF
Falling Slew =
< Figure : AC Input Test Signal Waveform>


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