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ADV212BBCZRL-115 Datasheet(PDF) 8 Page - Analog Devices |
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ADV212BBCZRL-115 Datasheet(HTML) 8 Page - Analog Devices |
8 / 44 page ADV212 Rev. B | Page 8 of 44 DREQ/DACK DMA MODE—SINGLE FIFO WRITE OPERATION Table 6. Parameter Mnemonic Min Typ Max Unit DREQ Pulse Width DREQPULSE 1 JCLK1 15 JCLK1 ns DACK Assert to Subsequent DREQ Delay t DREQ 2.5 JCLK1 3.5 × JCLK + 8.51 ns WE to DACK Setup t WESU 0 ns Data to DACK Deassert Setup tSU 2 ns Data to DACK Deassert Hold tHD 2 ns DACK Assert Pulse Width DACKLOW 2 JCLK1 ns DACK Deassert Pulse Width DACKHIGH 2 JCLK1 ns WE Hold After DACK Deassert t WEHD 0 ns WE Assert to FSRQ Deassert (FIFO Full) WFSRQ 1.5 JCLK1 2.5 × JCLK + 7.51 ns DACK to DREQ Deassert (DR × PULS = 0) t DREQRTN 2.5 JCLK1 3.5 × JCLK + 9.01 ns 1 For a definition of JCLK, see Figure 32. WE DACK DREQ HDATA 3 2 1 0 DREQPULSE tDREQ DACKHIGH DACKLOW tWE SU tSU tHD tWE HD Figure 5. Single Write for DREQ/DACK DMA Mode for Assigned DMA Channel (EDMOD0/EDMOD1[14:1] Not Programmed to a Value of 0000) WE DACK DREQ HDATA 0 1 2 tDREQ RTN DACKHIGH DACKLOW tWE SU tSU tHD tWE HD Figure 6. Single Write for DREQ/DACK DMA Mode for Assigned DMA Channel (EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000) |
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