AK5703EN datasheet(12/76 Pages) AKM

Part #	AK5703EN

Description	4-Channel 24-bit ADC with PLL & MIC-AMP

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Manufacturer	AKM [Asahi Kasei Microsystems]

Direct Link	http://www.akm.com

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[AK5703]

MS1537-E-00

2013/05

- 12 -

Parameter

Symbol

min

typ

max

Unit

External Master Mode

MCKI Input Timing

Frequency

256fs

fCLK

2.048

-

12.288

MHz

512fs

fCLK

4.096

-

12.288

MHz

1024fs

fCLK

8.192

-

12.288

MHz

Pulse Width Low

tCLKL

0.4/fCLK

-

s

Pulse Width High

tCLKH

0.4/fCLK

-

s

LRCK Output Timing

Frequency

fs

8

-

48

kHz

Stereo Mode: Duty Cycle

Duty

-

50

-

%

TDM64, TDM128 Mode:

I2S compatible: Pulse Width Low

tLRCKL

-

1/(4fs)

-

s

MSB justified: Pulse Width High

tLRCKH

-

1/(4fs)

-

s

BICK Output Timing

Period

BCKO1-0 bits = “00”

tBCK

-

1/(32fs)

-

s

BCKO1-0 bits = “01”

tBCK

-

1/(64fs)

-

s

BCKO1-0 bits = “10”

(TDM128 Mode)

tBCK

-

1/(128fs)

-

s

Duty Cycle

dBCK

-

50

-

%

Audio Interface Timing (Left justified & I2S)

Master Mode

BICK “

↓” to LRCK Edge (Note 15)

tMBLR

−40

-

40

ns

LRCK Edge to SDTO (MSB)

(Except I2S mode)

tLRD

−70

-

70

ns

BICK “

↓” to SDTO

tBSD

−70

-

70

ns

Slave Mode

LRCK Edge to BICK “

↑” (Note 15)

tLRB

50

-

ns

BICK “

↑” to LRCK Edge (Note 15)

tBLR

50

-

ns

LRCK Edge to SDTO (MSB)

(Except I2S mode)

tLRD

-

80

ns

BICK “

↓” to SDTO

tBSD

-

80

ns

Audio Interface Timing (TDM64 Mode)

Master Mode

BICK “

↓” to LRCK

tMBLR

-40

-

40

ns

BICK “

↓” to SDTOB (Note 16)

tBSD

-70

-

70

ns

Slave Mode

LRCK Edge to BICK “

↑” (Note 15)

tLRB

50

-

ns

BICK “

↑” to LRCK Edge (Note 15)

tBLR

50

-

ns

BICK “

↓” to SDTOB (Note 16)

tBSD

-

80

ns

Audio Interface Timing (TDM128 Mode)

Master Mode

BICK “

↓” to LRCK

tMBLR

-24

-

24

ns

BICK “

↓” to SDTOB (Note 16)

tBSD

-40

-

40

ns

Slave Mode

LRCK Edge to BICK “

↑” (Note 15)

tLRB

40

-

ns

BICK “

↑” to LRCK Edge (Note 15)

tBLR

40

-

ns

BICK “

↓” to SDTOB (Note 16)

tBSD

-

50

ns

Note 15. BICK rising edge must not occur at the same time as LRCK edge.

Note 16. SDTOA is fixed to “L”.

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