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IS46TR82560AL-15HBLA2 Datasheet(PDF) 11 Page - Integrated Silicon Solution, Inc

Part # IS46TR82560AL-15HBLA2
Description  256Mx8, 128Mx16 2Gb DDR3 SDRAM
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS46TR82560AL-15HBLA2 Datasheet(HTML) 11 Page - Integrated Silicon Solution, Inc

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IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
Integrated Silicon Solution, Inc.
– www.issi.com –
11
Rev. B1
8/08/2013
2.3.2 Mode Register MR0
The mode register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It controls burst length,
read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge Power-Down, which include
vendor specific options to make DDR3 SDRAM useful for various applications. The mode register is written by asserting
low on CS#, RAS#, CAS#, WE#, BA0, BA1, and BA2, while controlling the states of address pins according to the
following figure.
1. A14 and A13 must be programmed to 0 during MRS.
2.
WR (write recovery for autoprecharge)min in clock cycles is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up to the next integer:
WRmin[cycles] = Roundup(tWR[ns] / tCK[ns]). The WR value in the mode register must be programmed to be equal or larger than WRmin. The
programmed WR value is used with tRP to determine tDAL.
3. The table only shows the encodings for a given Cas Latency. For actual supported Cas Latency, please refer to speedbin tables for each
frequency
4. The table only shows the encodings for Write Recovery. For actual Write recovery timing, please refer to AC timing table.
Figure 2.3.2
— MR0 Definition
2.3.2.1 Burst Length, Type and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3
as shown in Figure 2.3.2. The ordering of accesses within a burst is determined by the burst length, burst type, and the
starting column address as shown in Table below. The burst length is defined by bits A0-A1. Burst length options include
fixed BC4, fixed BL8, and ‘on the fly’ which allows BC4 or BL8 to be selected coincident with the registration of a Read or
Write command via A12/BC#.
BA2
BA1
BA0
A14-A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0
0
0
0*1
PPD
WR
DLL
TM
CAS Latency
RBT
CL
BL
Mode Register 0
A8
DLL Reset
A7
mode
A3
Read Burst Type
A1
A0
BL
0
No
0
Nomal
0
Nibble Sequential
0
0
8 (Fixed)
1
Yes
1
Test
1
Interleave
0
1
BC4 or 8 (on the fly)
1
0
BC4 (Fixed)
A12
DLL Control for
Write recovery for autoprecharge
1
1
Reserved
Precharge PD
A11
A10
A9
WR(cycles)
0
Slow exit (DLL off)
0
0
0
Reserved
A6
A5
A4
A2
CAS Latency
1
Fast exit (DLL on)
0
0
1
5*2
0
0
0
0
Reserved
0
1
0
6*2
0
0
1
0
5
BA1 BA0
MR Select
0
1
1
7*2
0
1
0
0
6
0
0
MR0
1
0
0
8*2
0
1
1
0
7
0
1
MR1
1
0
1
10*2
1
0
0
0
8
1
0
MR2
1
1
0
12*2
1
0
1
0
9
1
1
MR3
1
1
1
14*2
1
1
0
0
10
1
1
1
0
11
0
0
0
1
12
0
0
1
1
13
0
1
0
1
14
0
1
1
1
Reserved
1
0
0
1
Reserved
1
0
1
1
Reserved
1
1
0
1
Reserved
1
1
1
1
Reserved


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