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MC68332GCFC20 Datasheet(PDF) 29 Page - Freescale Semiconductor, Inc |
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MC68332GCFC20 Datasheet(HTML) 29 Page - Freescale Semiconductor, Inc |
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29 / 88 page  MC68332 MOTOROLA MC68332TS/D 29 ADDR0 also affects the operation of the data multiplexer. During an operand transfer, ADDR[23:1] in- dicate the word base address of the portion of the operand to be accessed, and ADDR0 indicates the byte offset from the base. 3.4.11 Misaligned Operands CPU32 processor architecture uses a basic operand size of 16 bits. An operand is misaligned when it overlaps a word boundary. This is determined by the value of ADDR0. When ADDR0 = 0 (an even ad- dress), the address is on a word and byte boundary. When ADDR0 = 1 (an odd address), the address is on a byte boundary only. A byte operand is aligned at any address; a word or long-word operand is misaligned at an odd address. The CPU32 does not support misaligned operand transfers. The largest amount of data that can be transferred by a single bus cycle is an aligned word. If the MCU transfers a long-word operand via a 16-bit port, the most significant operand word is transferred on the first bus cycle and the least significant operand word on a following bus cycle. 3.4.12 Operand Transfer Cases The following table summarizes how operands are aligned for various types of transfers. OPn entries are portions of a requested operand that are read or written during a bus cycle and are defined by SIZ1, SIZ0, and ADDR0 for that bus cycle. NOTES: 1. Operands in parentheses are ignored by the CPU32 during read cycles. 2. Three-byte transfer cases occur only as a result of a long word to byte transfer. 3. The CPU32 does not support misaligned word or long-word transfers. 3.5 Chip Selects Typical microcontrollers require additional hardware to provide external chip-select signals. Twelve in- dependently programmable chip selects provide fast two-cycle access to external memory or peripher- als. Address block sizes of 2 Kbytes to 1 Mbyte can be selected. Table 11 Operand Alignment Transfer Case SIZ1 SIZ0 ADDR0 DSACK1 DSACK0 DATA [15:8] DATA [7:0] Byte to 8-Bit Port (Even/Odd) 0 1 X 1 0 OP0 (OP0) Byte to 16-Bit Port (Even) 0 1 0 0 X OP0 (OP0) Byte to 16-Bit Port (Odd) 0 1 1 0 X (OP0) OP0 Word to 8-Bit Port (Aligned) 1 0 0 1 0 OP0 (OP1) Word to 8-Bit Port (Misaligned)3 1 0 1 1 0 OP0 (OP0) Word to 16-Bit Port (Aligned) 1 0 0 0 X OP0 OP1 Word to 16-Bit Port (Misaligned)3 1 0 1 0 X (OP0) OP0 3 Byte to 8-Bit Port (Aligned)2 1 1 0 1 0 OP0 (OP1) 3 Byte to 8-Bit Port (Misaligned)2, 3 1 1 1 1 0 OP0 (OP0) 3 Byte to 16-Bit Port (Aligned)2 1 1 0 0 X OP0 OP1 3 Byte to 16-Bit Port (Misaligned)2, 3 1 1 1 0 X (OP0) OP0 Long Word to 8-Bit Port (Aligned) 0 0 0 1 0 OP0 (OP1) Long Word to 8-Bit Port (Misaligned)3 1 0 1 1 0 OP0 (OP0) Long Word to 16-Bit Port (Aligned) 0 0 0 0 X OP0 OP1 Long Word to 16-Bit Port (Misaligned)3 1 0 1 0 X (OP0) OP0 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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