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EP3C105F780I7 Datasheet(PDF) 92 Page - Altera Corporation |
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EP3C105F780I7 Datasheet(HTML) 92 Page - Altera Corporation |
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92 / 274 page  5–32 Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family PLL Reconfiguration Cyclone III Device Handbook July 2012 Altera Corporation Volume 1 Table 5–10 lists the PLL counter selection based on the corresponding PHASECOUNTERSELECT setting. To perform one dynamic phase shift step, you must perform the following procedures: 1. Set PHASEUPDOWN and PHASECOUNTERSELECT as required. 2. Assert PHASESTEP for at least two SCANCLK cycles. Each PHASESTEP pulse allows one phase shift. 3. Deassert PHASESTEP after PHASEDONE goes low. 4. Wait for PHASEDONE to go high. 5. Repeat steps 1 through 4 as many times as required to perform multiple phase- shifts. PHASEUPDOWN and PHASECOUNTERSELECT signals are synchronous to SCANCLK and must meet the tsu and th requirements with respect to the SCANCLK edges. 1 You can repeat dynamic phase-shifting indefinitely. For example, in a design where the VCO frequency is set to 1,000 MHz and the output clock frequency is set to 100 MHz, performing 40 dynamic phase shifts (each one yields 125 ps phase shift) results in shifting the output clock by 180, in other words, a phase shift of 5 ns. PHASESTEP Logic high enables dynamic phase shifting. Logic array or I/O pins PLL reconfiguration circuit SCANCLK Free running clock from core used in combination with PHASESTEP to enable or disable dynamic phase shifting. Shared with SCANCLK for dynamic reconfiguration. GCLK or I/O pins PLL reconfiguration circuit PHASEDONE When asserted, it indicates to core logic that the phase adjustment is complete and PLL is ready to act on a possible second adjustment pulse. Asserts based on internal PLL timing. Deasserts on rising edge of SCANCLK. PLL reconfiguration circuit Logic array or I/O pins Table 5–9. Dynamic Phase Shifting Control Signals (Part 2 of 2) Signal Name Description Source Destination Table 5–10. Phase Counter Select Mapping PHASECOUNTERSELECT [2] [1] [0] Selects 0 0 0 All Output Counters 0 0 1 M Counter 0 1 0 C0 Counter 0 1 1 C1 Counter 1 0 0 C2 Counter 1 0 1 C3 Counter 1 1 0 C4 Counter |
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