3.3-VLVTTL datasheet(10/34 Pages) ALTERA

Part #	3.3-VLVTTL

Description	This chapterdescribes the electric characteristics, switching characteristics,and I/O timing for Cyclone III devices. A glossary is also included for your reference

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Chapter 1: Cyclone III Device Datasheet

Electrical Characteristics

Cyclone III Device Handbook

July 2012

Altera Corporation

Volume 2

Schmitt Trigger Input

Cyclone III devices support Schmitt trigger input on TDI, TMS, TCK, nSTATUS, nCONFIG,

nCE

, CONF_DONE, and DCLK pins. A Schmitt trigger feature introduces hysteresis to the

input signal for improved noise immunity, especially for signal with slow edge rate.

Table 1–12 lists the hysteresis specifications across supported VCCIO range for Schmitt

trigger inputs in Cyclone III devices.

I/O Standard Specifications

The following tables list input voltage sensitivities (VIH and VIL), output voltage (VOH

and VOL), and current drive characteristics (IOH and IOL) for various I/O standards

supported by Cyclone III devices. Table 1–13 through Table 1–18 provide the I/O

standard specifications for Cyclone III devices.

Table 1–12. Hysteresis Specifications for Schmitt Trigger Input in Cyclone III Devices

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Unit

VSCHMITT

Hysteresis for Schmitt trigger

input

VCCIO = 3.3 V

200

—

mV

VCCIO = 2.5 V

200

—

mV

VCCIO = 1.8 V

140

—

mV

VCCIO = 1.5 V

110

—

mV

Table 1–13. Cyclone III Devices Single-Ended I/O Standard Specifications (1), (2)

I/O Standard

VCCIO (V)

VIL (V)

VIH (V)

VOL (V)

VOH (V)

IOL

(mA)

IOH

(mA)

Min

Typ

Max

Min

Max

Min

Max

Min

3.3-V LVTTL (3)

3.135

3.3

3.465

—

0.8

1.7

3.6

0.45

2.4

4

–4

3.3-V LVCMOS (3)

3.135

3.3

3.465

—

0.8

1.7

3.6

0.2

VCCIO – 0.2

2

–2

3.0-V LVTTL (3)

2.85

3.0

3.15

–0.3

0.8

1.7

VCCIO + 0.3

0.45

2.4

4

–4

3.0-V LVCMOS (3)

2.85

3.0

3.15

–0.3

0.8

1.7

VCCIO + 0.3

0.2

VCCIO – 0.2

0.1

–0.1

2.5-V LVTTL and

LVCMOS (3)

2.375

2.5

2.625

–0.3

0.7

1.7

3.6

0.4

2.0

1

–1

1.8-V LVTTL and

LVCMOS

1.71

1.8

1.89

–0.3

0.35 *

VCCIO

0.65 *

VCCIO

2.25

0.45

VCCIO –

0.45

2–2

1.5-V LVCMOS

1.425

1.5

1.575

–0.3

0.35 *

VCCIO

0.65 *

VCCIO

VCCIO + 0.3

0.25 *

VCCIO

0.75 *

VCCIO

2–2

1.2-V LVCMOS

1.14

1.2

1.26

–0.3

0.35 *

VCCIO

0.65 *

VCCIO

VCCIO + 0.3

0.25 *

VCCIO

0.75 *

VCCIO

2–2

3.0-V PCI

2.85

3.0

3.15

—

0.3 *

VCCIO

0.5 *

VCCIO

VCCIO + 0.3 0.1 * VCCIO

0.9 * VCCIO

1.5

–0.5

3.0-V PCI-X

2.85

3.0

3.15

—

0.35*

VCCIO

0.5 *

VCCIO

VCCIO + 0.3 0.1 * VCCIO

0.9 * VCCIO

1.5

–0.5

Notes to Table 1–13:

(1) For voltage referenced receiver input waveform and explanation of terms used in Table 1–13, refer to “Single-ended Voltage referenced I/O Standard”

in “Glossary” on page 1–27.

(2) AC load CL = 10 pF.

(3) For more detail about interfacing Cyclone III devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O standards, refer to AN 447: Interfacing Cyclone III

Devices with 3.3/3.0/2.5-V LVTTL and LVCMOS I/O Systems.

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