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MC68332GCFC16 Datasheet(PDF) 66 Page - Freescale Semiconductor, Inc |
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MC68332GCFC16 Datasheet(HTML) 66 Page - Freescale Semiconductor, Inc |
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66 / 88 page  MOTOROLA MC68332 66 MC68332TS/D 6.3 Pin Function The following table is a summary of the functions of the QSM pins when they are not configured for gen- eral-purpose I/O. The QSM data direction register (DDRQS) designates each pin except RXD as an in- put or output. 6.4 QSM Registers QSM registers are divided into four categories: QSM global registers, QSM pin control registers, QSPI submodule registers, and SCI submodule registers. The QSPI and SCI registers are defined in separate sections below. Writes to unimplemented register bits have no meaning or effect, and reads from unim- plemented bits always return a logic zero value. The module mapping bit of the SIM configuration register (SIMCR) defines the most significant bit (ADDR23) of the address, shown in each register figure as Y (Y = $7 or $F). This bit, concatenated with the rest of the address given, forms the absolute address of each register. Refer to the SIM section of this technical summary for more information about how the state of MM affects the system. 6.4.1 Global Registers The QSM global registers contain system parameters used by both the QSPI and the SCI submodules. These registers contain the bits and fields used to configure the QSM. The QSMCR contains parameters for the QSM/CPU/intermodule bus (IMB) interface. STOP — Stop Enable 0 = Normal QSM clock operation 1 = QSM clock operation stopped STOP places the QSM in a low-power state by disabling the system clock in most parts of the module. The QSMCR is the only register guaranteed to be readable while STOP is asserted. The QSPI RAM is not readable. However, writes to RAM or any register are guaranteed to be valid while STOP is assert- ed. STOP can be negated by the CPU and by reset. Pin Mode Pin Function MISO Master Serial Data Input to QSPI QSPI Pins Slave Serial Data Output from QSPI MOSI Master Serial Data Output from QSPI Slave Serial Data Input to QSPI SCK Master Clock Output from QSPI Slave Clock Input to QSPI PCS0/SS Master Input: Assertion Causes Mode Fault Output: Selects Peripherals Slave Input: Selects the QSPI PCS[3:1] Master Output: Selects Peripherals Slave None SCI Pins TXD Transmit Serial Data Output from SCI RXD Receive Serial Data Input to SCI QSMCR — QSM Configuration Register $YFFC00 15 14 13 12 11 10 9 8 7 6 5 4 3 0 STOP FRZ1 FRZ0 0 0 0 0 0 SUPV 0 0 0 IARB RESET: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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