Electronic Components Datasheet Search |
|
MAX19711ETN Datasheet(PDF) 9 Page - Maxim Integrated Products |
|
MAX19711ETN Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 36 page 10-Bit, 11Msps, Full-Duplex Analog Front-End _______________________________________________________________________________________ 9 ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 11MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, VFS = 410mV, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS BUFFERED EXTERNAL REFERENCE (external VREFIN = 1.024V applied; VREFP, VREFN, VCOM levels are generated internally) Reference Input Voltage VREFIN 1.024 V Differential Reference Output VDIFF VREFP - VREFN 0.512 V Common-Mode Output Voltage VCOM VDD / 2 V Maximum REFP/REFN/COM Source Current ISOURCE 2mA Maximum REFP/REFN/COM Sink Current ISINK 2mA REFIN Input Current -0.7 µA REFIN Input Resistance 500 k Ω DIGITAL INPUTS (CLK, SCLK, DIN, CS/WAKE, DA9–DA0) Input High Threshold VINH 0.7 x OVDD V Input Low Threshold VINL 0.3 x OVDD V CLK, SCLK, DIN, CS/WAKE = OGND or OVDD -1 +1 DA9–DA0 = OVDD -1 +1 Input Leakage DIIN DA9–DA0 = OGND -5 +5 µA Input Capacitance DCIN 5pF DIGITAL OUTPUTS (AD9–AD0, DOUT) Output-Voltage Low VOL ISINK = 200µA 0.2 x OVDD V Output-Voltage High VOH ISOURCE = 200µA 0.8 x OVDD V Tri-State Leakage Current ILEAK -1 +1 µA Tri-State Output Capacitance COUT 5pF Note 1: Specifications from TA = +25°C to +85°C guaranteed by production test. TA < +25°C guaranteed by design and characteri- zation. Note 2: The minimum clock frequency (fCLK) for the MAX19711 is 2MHz (typ). The minimum aux-ADC sample rate clock frequency (ACLK) is determined by fCLK and the chosen aux-ADC clock-divider value. The minimum aux-ADC ACLK > 2MHz / 128 = 15.6kHz. The aux-ADC conversion time does not include the time to clock the serial data out of DOUT. The maximum con- version time (for no averaging, NAVG = 1) will be tCONV (max) = (12 x 1 x 128) / 2MHz = 768µs. Note 3: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude of the digital outputs. SINAD and THD are calculated using HD2 through HD6. Note 4: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the sec- ond channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second channel FFT test tones. Note 5: Amplitude and phase matching are measured by applying the same signal to each channel, and comparing the two output signals using a sine-wave fit. Note 6: Guaranteed by design and characterization. |
Similar Part No. - MAX19711ETN |
|
Similar Description - MAX19711ETN |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |