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MM74C89N Datasheet(PDF) 4 Page - Fairchild Semiconductor |
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MM74C89N Datasheet(HTML) 4 Page - Fairchild Semiconductor |
4 / 6 page www.fairchildsemi.com 4 AC Electrical Characteristics (Note 2) TA = 25°C, CL = 50 pF, unless otherwise noted Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics application note, AN-90. Symbol Parameter Conditions Min Typ Max Units tpd Propagation Delay from VCC = 5V 270 500 ns Memory Enable VCC = 10V 100 220 ns tACC Access Time from VCC = 5V 350 650 ns Address Input VCC = 10V 130 280 ns tSA Address Setup Time VCC = 5V 150 ns VCC = 10V 60 ns tHA Address Hold Time VCC = 5V 60 ns VCC = 10V 40 ns tME Memory Enable Pulse Width VCC = 5V 400 250 ns VCC = 10V 150 90 ns tSR Write Enable Setup VCC = 5V 0 ns Time for a Read VCC = 10V 0 ns tWS Write Enable Setup VCC = 5V tME ns Time for a Write VCC = 10V tME ns tWE Write Enable Pulse Width VCC = 5V, tWS = 0 300 160 ns VCC = 10V, tWS = 0 100 60 ns tHD Data Input Hold Time VCC = 5V 50 ns VCC = 10V 25 ns tSD Data Input Setup VCC = 5V 50 ns VCC = 10V 25 ns t1H, t0H Propagation Delay from a Logical VCC = 5V, CL = 5 pF, RL = 10k 180 300 ns “1” or Logical “0” to the High VCC = 10V, CL = 5 pF, RL = 10k −85 120 ns Impedance State from Memory Enable t1H, t0H Propagation Delay from a Logical VCC = 50V, CL = 5 pF, RL = 10k 180 300 ns “1” or Logical “0” to the High VCC = 10V, CL = 5 pF, RL = 10k 85 120 ns Impedance State from Write Enable CIN Input Capacity Any Input (Note 3) 5 pF COUT Output Capacity Any Output (Note 3) 6.5 pF CPD Power Dissipation Capacity (Note 4) 230 pF |
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