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MM74HC148M Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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MM74HC148M Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 8 page October 1987 Revised February 1999 © 1999 Fairchild Semiconductor Corporation DS009390.prf www.fairchildsemi.com MM74HC148 8-3 Line Priority Encoder General Description The MM74HC148 priority encoder utilizes advanced sili- con-gate CMOS technology. It has the high noise immunity and low power consumption typical of CMOS circuits, as well as the speeds and output drive similar to LB-TTL. This priority encoder accepts 8 input request lines 0–7 and outputs 3 lines A0–A2. The priority encoding ensures that only the highest order data line is encoded. Cascading cir- cuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry. All data inputs and outputs are active at the low logic level. All inputs are protected from damage due to static dis- charge by internal diode clamps to VCC and ground. Features s Typical propagation delay: 13 ns s Wide supply voltage range: 2V–6V Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC and TSSOP Truth Table H = HIGH L = LOW X = Irrelevant Order Number Package Number Package Description MM74HC148M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM74HC148MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC148N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Inputs Outputs EI 012 345 67 A2 A1 A0 GS EO H XXX XXX XX H H H H H L H H HHH HHH H H H H L L XXX XXX X L L L L L H L XXX XXX L H L L H L H L XXX XX L H H L H L L H L XXX X L H H H L H H L H L XXX L H H H H H L L L H L X X L HH HHH H L H L H L X L HHH HHH H H L L H L L H HHH HHH H H H L H |
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