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EP2AGX45DF25I3N Datasheet(PDF) 58 Page - Altera Corporation |
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EP2AGX45DF25I3N Datasheet(HTML) 58 Page - Altera Corporation |
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58 / 78 page  1–58 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum July 2012 Altera Corporation Embedded Memory Block Specifications Table 1–48 lists the embedded memory block specifications for Arria II GX devices. Double mode 1 440 380 MHz Notes to Table 1–47: (1) Maximum is for fully pipelined block with Round and Saturation disabled. (2) Maximum for loopback input registers disabled, Round and Saturation disabled, and pipeline and output registers enabled. Table 1–47. DSP Block Performance Specifications for Arria II GZ Devices (Note 1) (Part 2 of 2) Mode Resources Used Performance Unit Number of Multipliers –3 –4 Table 1–48. Embedded Memory Block Performance Specifications for Arria II GX Devices Memory Mode Resources Used Performance Unit ALUTs Embedded Memory I3 C4 C5,I5 C6 Memory Logic Array Block (MLAB) Single port 64 × 10 0 1 450 500 450 378 MHz Simple dual-port 32 × 20 single clock 0 1 270 500 450 378 MHz Simple dual-port 64 × 10 single clock 0 1 428 500 450 378 MHz M9K Block Single-port 256 × 36 0 1 360 400 360 310 MHz Single-port 256 × 36, with the read-during-write option set to Old Data 0 1 250 280 250 210 MHz Simple dual-port 256 × 36 single CLK 0 1 360 400 360 310 MHz Single-port 256 × 36 single CLK, with the read-during-write option set to Old Data 0 1 250 280 250 210 MHz True dual port 512 × 18 single CLK 0 1 360 400 360 310 MHz True dual-port 512 × 18 single CLK, with the read-during-write option set to Old Data 0 1 250 280 250 210 MHz Min Pulse Width (clock high time) — — 900 850 950 1130 ps Min Pulse Width (clock low time) — — 730 690 770 920 ps |
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