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EP1SGX40FF1020C5N Datasheet(PDF) 53 Page - Altera Corporation

Part # EP1SGX40FF1020C5N
Description  Section I. Stratix GX Device Family Data Sheet
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1SGX40FF1020C5N Datasheet(HTML) 53 Page - Altera Corporation

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Altera Corporation
3–3
August 2005
Stratix GX Device Handbook, Volume 1
Source-Synchronous Signaling With DPA
Figure 3–1. Stratix GX High-Speed Interface Deserialized in
×10 Mode
Notes to Figure 3–1:
(1)
W = 1, 2, 4, 7, 8, or 10.
J = 4, 7, 8, or 10 for non-DPA (J = 8 or 10 for DPA).
W does not have to equal J. When J = 1 or 2, the deserializer is bypassed. When J = 2, the device uses DDRIO registers.
(2)
This figure does not show additional circuitry for clock or data manipulation.
Figure 3–2. Receiver Timing Diagram
Stratix GX Differential I/O Transmitter Operation
You can configure any of the Stratix GX differential output channels as a
transmitter channel. The differential transmitter serializes outbound
parallel data.
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
Stratix GX
Logic Array
Receiver Circuit
Serial Shift
Registers
Parallel
Registers
Parallel
Registers
Fast
PLL (2)
RXIN+
RXIN
−
RXCLKIN+
RXCLKIN
−
×W
×W/J (1)
RXLOADEN
TXLOADEN
RXLOADEN
Internal
×1 clock
Internal
×10 clock
Receiver
data input
n – 1
n – 0
9
8
7
6
5
4
3
2
1
0


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