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EP1SGX40DF1020I5N Datasheet(PDF) 37 Page - Altera Corporation |
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EP1SGX40DF1020I5N Datasheet(HTML) 37 Page - Altera Corporation |
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37 / 272 page  Altera Corporation 2–27 June 2006 Stratix GX Device Handbook, Volume 1 Stratix GX Transceivers Parallel Loopback The parallel loopback mode exercises the digital logic portion of the transceiver data path. The analog portions are not use in the loopback path. The received data is not retimed. Figure 2–22 shows the data path in parallel loopback mode. This option is not dynamically switchable. Reception of an external signal is not possible in this mode. Figure 2–22. Data Path in Parallel Loopback Mode Reverse Serial Loopback The reverse serial loopback exercises the analog portion of the transceiver. This loopback mode is dynamically switchable through the tx_srlpbk port on a channel by channel basis. Asserting rxanalogreset in reverse serial loopback mode powers down the receiver buffer and CRU, preventing data loopback. Figure 2–23 shows the data path in reverse serial loopback mode. Clock Recovery Unit Word Aligner BIST PRBS Verifier BIST Incremental Verifier Channel Aligner Rate Matcher BIST Generator Byte Deserializer Phase Compensation FIFO Phase Compensation FIFO Byte Serializer Serializer BIST PRBS Generator 8B/10B Encoder 8B/10B Decoder Deserializer Non-Active Path Active Path |
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