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EP1SGX40FF1020I6N Datasheet(PDF) 59 Page - Altera Corporation |
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EP1SGX40FF1020I6N Datasheet(HTML) 59 Page - Altera Corporation |
59 / 272 page Altera Corporation 3–9 August 2005 Stratix GX Device Handbook, Volume 1 Source-Synchronous Signaling With DPA Figure 3–7. PLL & Channel Layout in EP1SGX40 Devices Notes (1), (2), (3) Notes to Figure 3–7: (1) Corner PLLs do not support DPA. (2) Not all eight phases are used by the receiver channel or transmitter channel in non-DPA mode. (3) The center PLLs can only clock 20 transceivers in either direction. Using Fast PLL2, you can clock a total of 40 transceivers, 20 in each direction. Fast PLL 1 Fast PLL 2 1 Receiver 1 Receiver 1 Transmitter 1 Transmitter 1 Receiver 1 Receiver 1 Transmitter 1 Transmitter INCLK0 PLL (1) CLKIN PLL (1) CLKIN INCLK1 23 Rows 22 Rows 8 Eight-Phase Clock Eight-Phase Clock 8 |
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