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EP1SGX40FF1020I6N Datasheet(PDF) 43 Page - Altera Corporation |
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EP1SGX40FF1020I6N Datasheet(HTML) 43 Page - Altera Corporation |
43 / 272 page Altera Corporation 2–33 June 2006 Stratix GX Device Handbook, Volume 1 Stratix GX Transceivers The receiver PLL can also drive the fast regional, regional clocks, and local routing adjacent to the associated transceiver block. Figures 2–28 through 2–31 show which fast regional and regional clock resource can be used by the recovered clock. In the EP1SGX25 device, the receiver PLL recovered clocks from transceiver blocks 0 and 1 drive RCLK[1..0] while transceiver blocks 2 and 3 drive RCLK[7..6]. The regional clocks feed logic in their associated regions. Figure 2–28. EP1SGX25 Receiver PLL Recovered Clock to Regional Clock Connection In addition, the receiver PLL’s recovered clocks can drive fast regional lines (FCLK) as shown Figure 2–29. The fast regional clocks can feed logic in their associated regions. Stratix GX Transceiver Blocks PLD RCLK[11..10] Block 0 Block 1 Block 2 Block 3 RCLK[9..8] |
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