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EP1SGX40CF1020C7N Datasheet(PDF) 24 Page - Altera Corporation |
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EP1SGX40CF1020C7N Datasheet(HTML) 24 Page - Altera Corporation |
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24 / 272 page  2–14 Altera Corporation Stratix GX Device Handbook, Volume 1 June 2006 Figure 2–10 shows a diagram of the receiver input buffer, which contains: ■ Programmable termination ■ Programmable equalizer Figure 2–10. Receiver Input Buffer Programmable Termination The programmable termination can be statically set in the Quartus II software. Figure 2–11 shows the setup for programmable receiver termination. Figure 2–11. Programmable Receiver Termination If you use external termination, then the receiver must be externally terminated and biased to 1.1 V. Figure 2–12 shows an example of an external termination/biasing circuit. Programmable Termination Input Pins Differential Input Buffer Programmable Equalizer Differential Input Buffer 50, 60, or 75 Ω 50, 60, or 75 Ω VCM |
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