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EP1SGX40CF1020I7N Datasheet(PDF) 97 Page - Altera Corporation

Part # EP1SGX40CF1020I7N
Description  Section I. Stratix GX Device Family Data Sheet
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1SGX40CF1020I7N Datasheet(HTML) 97 Page - Altera Corporation

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Altera Corporation
4–31
February 2005
Stratix GX Device Handbook, Volume 1
Stratix GX Architecture
The read and write operation of the memory is controlled by the WREN
signal, which sets the ports into either read or write modes. There is no
separate read enable (RE) signal.
Writing into RAM is controlled by both the WREN and byte enable
(byteena) signals for each port. The default value for the byteena
signal is high, in which case writing is controlled only by the WREN signal.
The byte enables are available for the ×18, ×36, and ×72 modes. In the
×144 simple dual-port mode, the two sets of byteena signals
(byteena_a and byteena_b) are combined to form the necessary
16 byte enables. Tables 4–9 and 4–10 summarize the byte selection.
Table 4–8. M-RAM Block Configurations (True Dual-Port)
Port A
Port B
64K × 9
32K × 18
16K × 36
8K × 72
64K
× 9
vvv
v
32K
× 18
vvv
v
16K
× 36
vvv
v
8K
× 72
vvv
v
Table 4–9. Byte Enable for M-RAM Blocks Notes (1), (2)
byteena[3..0]
datain ×18
datain ×36
datain ×72
[0] = 1
[8..0]
[8..0]
[8..0]
[1] = 1
[17..9]
[17..9]
[17..9]
[2] = 1
[26..18]
[26..18]
[3] = 1
[35..27]
[35..27]
[4] = 1
[44..36]
[5] = 1
[53..45]
[6] = 1
[62..54]
[7] = 1
[71..63]


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