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EP1SGX40CF1020I7N Datasheet(PDF) 34 Page - Altera Corporation |
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EP1SGX40CF1020I7N Datasheet(HTML) 34 Page - Altera Corporation |
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34 / 272 page  2–24 Altera Corporation Stratix GX Device Handbook, Volume 1 June 2006 XAUI Mode In XAUI mode, the rate matcher adheres to clause 48 of the IEEE 802.3ae specification for clock rate compensation. The rate matcher performs clock compensation on columns of /R/ (/K28.0/), denoted by //R//. An //R// is added or deleted automatically based on the number of words in the FIFO buffer. 8B/10B Decoder The 8B/10B decoder converts the 10-bit encoded code group into 8-bit data and 1 control bit. The 8B/10B decoder can be bypassed. The following is a diagram of the conversion from a 10-bit encoded code group into 8-bit data + 1-bit control. Figure 2–20. 8B/10B Decoder Conversion There are two optional error status ports available in the 8B/10B decoder, rx_errdetect and rx_disperr. Table 2–7 shows the values of the ports from a given error. These status signals are aligned with the code group in which the error occurred. Table 2–7. Error Signal Values Types of Errors rx_errdetect rx_disperr No errors 1’b0 1’b0 Invalid code groups 1’b1 1’b0 Disparity errors 1’b1 1’b1 98 76 5 4 3 2 1 0 8b-10b conversion jh g f i e d c b a MSB received last LSB received first 76 5 4 3 2 1 0 HG F E D C B A + ctrl Parallel data |
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