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SI5330H-A00220-GM Datasheet(PDF) 1 Page - Silicon Laboratories |
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SI5330H-A00220-GM Datasheet(HTML) 1 Page - Silicon Laboratories |
1 / 20 page Rev. 1.0 4/12 Copyright © 2012 by Silicon Laboratories Si5330 Si5330 1.8/2.5/3.3 V L OW-J ITTER, L OW-S KEW C LOCK B UFFER/L EVEL TRANSLATOR Features Applications Functional Block Diagram Supports single-ended or differential input clock signals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Provides signal level translation Differential to single-ended Single-ended to differential Differential to differential Single-ended to single-ended Wide frequency range LVPECL, LVDS: 5 to 710 MHz HCSL: 5 to 250 MHz SSTL, HSTL: 5 to 350 MHz CMOS: 5 to 200 MHz Additive jitter: 150 fs RMS typ Output-output skew: 100 ps Propagation delay: 2.5 ns typ Single core supply with excellent PSRR: 1.8, 2.5, or 3.3 V Output driver supply voltage independent of core supply: 1.5, 1.8, 2.5, or 3.3 V Loss of Signal (LOS) indicator allows system clock monitoring Output Enable (OEB) pin allows glitchless control of output clocks Low power: 10 mA typical core current Industrial temperature range: –40 to +85 °C Small size: 24-lead, 4 x 4 mm QFN High Speed Clock Distribution Ethernet Switch/Router SONET / SDH PCI Express 2.0/3.0 Fibre Channel MSAN/DSLAM/PON Telecom Line Cards Single-ended or Differential Single-ended or Differential Si5330 OEB Control LOS IN VDD VDDO0 CLK0 VDDO1 CLK1 VDDO2 CLK2 VDDO3 CLK3 Ordering Information: See page 14. Pin Assignments IN3 IN2 IN1 CLK2B CLK2A VDDO2 VDDO1 CLK1B CLK1A RSVD_GND GND GND RSVD_GND RSVD_GND 24 23 22 21 20 19 7 8 9 10 11 12 |
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