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EP1SGX40DF1020I7ES Datasheet(PDF) 54 Page - Altera Corporation |
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EP1SGX40DF1020I7ES Datasheet(HTML) 54 Page - Altera Corporation |
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54 / 272 page  3–4 Altera Corporation Stratix GX Device Handbook, Volume 1 August 2005 Introduction The logic array sends parallel data to the SERDES transmitter circuit when the TXLOADEN signal is asserted. This signal is generated by the high-speed counter circuitry of the logic array low-frequency clock’s rising edge. The data is then transferred from the parallel register into the serial shift register by the TXLOADEN signal on the third rising edge of the high-frequency clock. Figure 3–3 shows the block diagram of a single SERDES transmitter channel and Figure 3–4 shows the timing relationship between the data and clocks in Stratix GX devices in ×10 mode. W is the low-frequency multiplier and J is the data parallelization division factor. Figure 3–3. Stratix GX High-Speed Interface Serialized in ×10 Mode Figure 3–4. Transmitter Timing Diagram PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Stratix GX Logic Array Transmitter Circuit Parallel Register Serial Register Fast PLL TXOUT+ TXOUT − ×W TXLOADEN TXLOADEN Internal ×1 clock Internal ×10 clock Receiver data input n – 1 n – 0 9 8 7 6 5 4 3 2 1 0 |
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