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EP1SGX40DF1020I7ES Datasheet(PDF) 60 Page - Altera Corporation |
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EP1SGX40DF1020I7ES Datasheet(HTML) 60 Page - Altera Corporation |
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60 / 272 page  3–10 Altera Corporation Stratix GX Device Handbook, Volume 1 August 2005 Introduction DPA Operation The DPA receiver circuitry contains the dynamic phase selector, the deserializer, the synchronizer, and the data realigner (see Figure 3–8). This section describes the DPA operation, synchronization and data realignment. In the SERDES with DPA mode, the source clock is fed to the fast PLL through the dedicated clock input pins. This clock is multiplied by the multiplication value W to match the serial data rate. For information on the deserializer, see “Principles of SERDES Operation” on page 3–1. Figure 3–8. DPA Receiver Circuit Note to Figure 3–8: (1) These are phase-matched and retimed high-speed clocks and data. The dynamic phase selector matches the phase of the high-speed clock and data before sending them to the deserializer. The fast PLL supplies eight phases of the same clock (each a separate tap from a four-stage differential VCO) to all the differential channels associated with the selected fast PLL. The DPA circuitry inside each channel locks to a phase closest to the serial data’s phase and sends the retimed data and the selected clock to the deserializer. The DPA circuitry automatically performs this operation and is not something you select. Each channel’s DPA circuit can independently choose a different clock phase. The data phase detection and the clock phase selection process is automatic and continuous. The eight phases of the clock give the DPA circuit a granularity of one eighth of the unit interval (UI) or 125 ps at 1Gbps. Figure 3–9 illustrates the clocks generated by the fast PLL circuitry and their relationship to a data stream. rxin+ rxin- inclk+ inclk - Fast PLL Dynamic Phase Selector Deserializer Parallel Clock Synchronizer Data Realigner ×W Clock (1) ×1 Clock Serial Data (1) Stratix GX Logic Array DPA Receiver Circuit GCLK RCLK Reset 8 10 10 dpll_reset |
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