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EP1SGX40DF1020I7ES Datasheet(PDF) 61 Page - Altera Corporation

Part # EP1SGX40DF1020I7ES
Description  Section I. Stratix GX Device Family Data Sheet
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1SGX40DF1020I7ES Datasheet(HTML) 61 Page - Altera Corporation

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Altera Corporation
3–11
August 2005
Stratix GX Device Handbook, Volume 1
Source-Synchronous Signaling With DPA
Figure 3–9. Fast PLL Clocks & Data Input
Protocols, Training Pattern & DPA Lock Time
The dynamic phase aligner uses a fast PLL for clock multiplication, and
the dynamic phase selector for the phase detection and alignment. The
dynamic phase aligner uses the high-speed clock out of the dynamic
phase selector to deserialize high-speed data and the receiver's source
synchronous operations.
At each rising edge of the clock, the dynamic phase selector determines
the phase difference between the clock and the data and automatically
compensates for the phase difference between the data and clock.
Clock A
Data input
Clock B
Clock C
Clock D
Clock C'
Clock D'
Clock A'
Clock B'
D0
D1
D2
D3
D4
D5
D
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