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EP1SGX40DF1020I7ES Datasheet(PDF) 68 Page - Altera Corporation |
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EP1SGX40DF1020I7ES Datasheet(HTML) 68 Page - Altera Corporation |
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68 / 272 page  4–2 Altera Corporation Stratix GX Device Handbook, Volume 1 February 2005 Logic Array Blocks M4K RAM blocks, or DSP blocks from the left and right can also drive an LAB’s local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each LE can drive 30 other LEs through fast local and direct link interconnects. Figure 4–2 shows the direct link connection. Figure 4–2. Direct Link Connection LAB Control Signals Each LAB contains dedicated logic for driving control signals to its LEs. The control signals include two clocks, two clock enables, two asynchronous clears, synchronous clear, asynchronous preset/load, synchronous load, and add/subtract control signals. This gives a maximum of 10 control signals at a time. Although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. Each LAB can use two clocks and two clock enable signals. Each LAB’s clock and clock enable signals are linked. For example, any LE in a particular LAB using the labclk1 signal also uses labclkena1. If the LAB uses both the rising and falling edges of a clock, it also uses both LAB-wide clock signals. De-asserting the clock enable signal turns off the LAB-wide clock. LAB Direct link interconnect to right Direct link interconnect from right LAB, TriMatrix memory block, DSP block, or IOE output Direct link interconnect from left LAB, TriMatrix memory block, DSP block, or IOE output Local Interconnect Direct link interconnect to left |
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