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EP1SGX40FF1020I7ES Datasheet(PDF) 55 Page - Altera Corporation |
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EP1SGX40FF1020I7ES Datasheet(HTML) 55 Page - Altera Corporation |
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55 / 272 page  Altera Corporation 3–5 August 2005 Stratix GX Device Handbook, Volume 1 Source-Synchronous Signaling With DPA DPA Block Overview Each Stratix GX receiver channel features a DPA block. The block contains a dynamic phase selector for phase detection and selection, a SERDES, a synchronizer, and a data realigner circuit. You can bypass the dynamic phase aligner without affecting the basic source-synchronous operation of the channel by using a separate deserializer shown in Figure 3–5. The dynamic phase aligner uses both the source clock and the serial data. The dynamic phase aligner automatically and continuously tracks fluctuations caused by system variations and self-adjusts to eliminate the phase skew between the multiplied clock and the serial data. Figure 3–5 shows the relationship between Stratix GX source-synchronous circuitry and the Stratix GX source-synchronous circuitry with DPA. Figure 3–5. Source-Synchronous DPA Circuitry Note to Figure 3–5: (1) Both deserializers are identical. The deserializer operation is described in the “Principles of SERDES Operation” section. PLL Dynamic Phase Aligner Deserializer Stratix GX Logic Array Receiver Circuit ×W ×1 rx_in+ rx_in- rx_inclock_p rx_inclock_n 8 Deserializer (1) (1) |
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