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EP1SGX40FF1020I7ES Datasheet(PDF) 67 Page - Altera Corporation |
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EP1SGX40FF1020I7ES Datasheet(HTML) 67 Page - Altera Corporation |
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67 / 272 page  Altera Corporation 4–1 February 2005 4. Stratix GX Architecture Logic Array Blocks Each LAB consists of 10 LEs, LE carry chains, LAB control signals, local interconnect, LUT chain, and register chain connection lines. The local interconnect transfers signals between LEs in the same LAB. LUT chain connections transfer the output of one LE’s LUT to the adjacent LE for fast sequential LUT connections within the same LAB. Register chain connections transfer the output of one LE’s register to the adjacent LE’s register within an LAB. The Quartus® II Compiler places associated logic within an LAB or adjacent LABs, allowing the use of local, LUT chain, and register chain connections for performance and area efficiency. Figure 4–1 shows the Stratix® GX LAB. Figure 4–1. Stratix GX LAB Structure LAB Interconnects The LAB local interconnect can drive LEs within the same LAB. The LAB local interconnect is driven by column and row interconnects and LE outputs within the same LAB. Neighboring LABs, M512 RAM blocks, Direct link interconnect from adjacent block Direct link interconnect to adjacent block Row Interconnects of Variable Speed & Length Column Interconnects of Variable Speed & Length Three-Sided Architecture—Local Interconnect is Driven from Either Side by Columns & LABs, & from Above by Rows Local Interconnect LAB Direct link interconnect from adjacent block Direct link interconnect to adjacent block SGX51004-1.0 |
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