RECOMMENDED OPERATING CONDITIONS

(1)

ELECTRICAL CHARACTERISTICS

CDCVF2510A

MIN

MAX

UNIT

Supply voltage

3

3.6

V

High-level input voltage

2

V

Low-level input voltage

0.8

V

Input voltage

0

V

High-level output current

–12

mA

Low-level output current,

12

mA

20

175

MHz

Input clock duty cycle

40%

60%

Stabilization time

1

ms

(1)

Unused inputs must be held high or low to prevent them from floating.

(2)

Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be

obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for

propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not

apply for input modulation under SSC application.

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Input clamp voltage

3 V

-1.2

V

MIN to MAX

High-level output voltage

3 V

2.1

V

3 V

2.4

MIN to MAX

0.2

Low-level output voltage

3 V

0.8

V

3 V

0.55

3 V

–28

High-level output current

3.3 V

–36

mA

3.6 V

-8

3 V

30

Low-level output current

3.3 V

40

mA

3.6 V

10

Input current

3.6 V

±5

µA

Supply current

(2)

3.6 V, 0 V

40

µA

(static, output not switching)

Outputs: low or high

Change in supply current

3.3 V to 3.6 V

500

µA

GND

Input capacitance

3.3 V

2.5

pF

Output capacitance

3.3 V

2.8

pF

(1)

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

(2)

Copyright © 2004–2009, Texas Instruments Incorporated

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