50:

SDO, SCO/SDO2

50:

SDO, SCO/SDO2

SDI

SDI

2 k:

80 k:

1 pF

20 k:

2 k:

LMH0046

www.ti.com

SNLS222F – APRIL 2006 – REVISED APRIL 2013

Figure 4. Equivalent SDI Input Circuit (SDI, SDI)

Figure 5. Equivalent SDO Output Circuit (SDO, SDO, SCO/SDO2, SCO/SDO2)

OPERATING SERIAL DATA RATES

This device operates at serial data rates of 143 Mbps, 270 Mbps, 1483 Mbps and 1485 Mbps. The device does

not lock to harmonics of these rates. The device does not lock and automatically enters the reclocker bypass

mode for the following data rates: 177 Mbps, 360 Mbps, and 540 Mbps.

SERIAL DATA CLOCK/SERIAL DATA 2 OUTPUT

The Serial Data Clock/Serial Data 2 Output is controlled by the SCO_EN input and provides either a second

retimed serial data output or a low jitter differential clock output appropriate to the serial data rate being

processed. When operating as a serial clock output, the rising edge of the clock will be positioned within the

corresponding serial data bit interval within 10% of the center of the data interval.

Differential output SCO/SDO2 functions as the second serial data output when the SCO_EN input is a logic-low

level. This output functions as the serial data-rate clock output when the SCO_EN input is a logic-high level. The

SCO_EN input has an internal pull-down device and the default state of SCO_EN is low (serial data output 2

enabled). SCO/SDO2 is muted when the MUTE input is a logic low level. When the Bypass mode is activated

and this output is functioning as a serial clock output, the output will also be muted.

Copyright © 2006–2013, Texas Instruments Incorporated

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