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AD977ARS Datasheet(PDF) 4 Page - Analog Devices |
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AD977ARS Datasheet(HTML) 4 Page - Analog Devices |
4 / 24 page –4– REV. D AD977/AD977A–SPECIFICATIONS (Both Specs) A, B, C Grades Parameter Conditions Min Typ Max Unit DIGITAL INPUTS Logic Levels VIL –0.3 +0.8 V VIH 2.0 VDIG + 0.3 V IIL ±10 µA IIH ±10 µA DIGITAL OUTPUTS Data Format Serial 16-Bits Data Coding Binary Two’s Complement or Straight Binary Pipeline Delay Conversion Results Only Available after Completed Conversion V OL I SINK = 1.6 mA 0.4 V V OH I SOURCE = 500 µA4 V POWER SUPPLIES Specified Performance V DIG 4.75 5 5.25 V V ANA 4.75 5 5.25 V I DIG 4mA I ANA 11 mA Power Dissipation PWRD LOW 100 mW PWRD HIGH 50 µW TEMPERATURE RANGE Specified Performance T MIN to TMAX –40 +85 °C Specifications subject to change without notice. TIMING SPECIFICATIONS AD977A AD977 Symbol Min Typ Max Min Typ Max Unit Convert Pulsewidth t1 50 50 ns R/ C, CS to BUSY Delay t2 83 83 ns BUSY LOW Time t3 4.0 8.0 µs BUSY Delay after End of Conversion t4 50 50 ns Aperture Delay t5 40 40 ns Conversion Time t6 3.8 4.0 7.6 8.0 µs Acquisition Time t7 1.0 2.0 µs Throughput Time t6 + t7 510 µs R/ C Low to DATACLK Delay t8 220 350 ns DATACLK Period t9 220 450 ns DATA Valid Setup Time t10 50 100 ns DATA Valid Hold Time t11 20 20 ns EXT. DATACLK Period t12 66 100 ns EXT. DATACLK HIGH t13 20 20 ns EXT. DATACLK LOW t14 30 30 ns R/ C, CS to EXT. DATACLK Setup Time t15 20 t12 + 5 20 t12 + 5 ns R/ C to CS Setup Time t16 10 10 ns EXT. DATACLK to SYNC Delay t17 15 66 15 66 ns EXT. DATACLK to DATA Valid Delay t18 25 66 25 66 ns CS to EXT. DATACLK Rising Edge Delay t19 10 10 ns Previous DATA Valid after CS, R/C Low t20 3.5 7.5 µs BUSY to EXT. DATACLK Setup Time t21 55 ns Final EXT. DATACLK to BUSY Rising Edge t22 1.7 3.5 µs TAG Valid Setup Time t23 00 ns TAG Valid Hold Time t24 20 20 ns Specifications subject to change without notice. (AD977A: FS = 200 kHz, AD977: FS = 100 kHz, VDIG = VANA = 5 V, –40 C to +85 C) |
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