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AD7654 Datasheet(PDF) 5 Page - Analog Devices

Part # AD7654
Description  18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7654 Datasheet(HTML) 5 Page - Analog Devices

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AD7679
Rev. A | Page 5 of 28
TIMING SPECIFICATIONS
–40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Refer to Figure 32 and Figure 33
Convert Pulsewidth
t1
10
ns
Time between Conversions
t2
1.75
μs
CNVST LOW to BUSY HIGH Delay
t3
35
ns
BUSY HIGH All Modes Except Master Serial Read after Convert
t4
1.5
μs
Aperture Delay
t5
2
ns
End of Conversion to BUSY LOW Delay
t6
10
ns
Conversion Time
t7
1.5
μs
Acquisition Time
t8
250
ns
RESET Pulsewidth
t9
10
ns
Refer to Figure 34, Figure 35, and Figure 36 (Parallel Interface Modes)
CNVST LOW to Data Valid Delay
t10
1.5
μs
Data Valid to BUSY LOW Delay
t11
20
ns
Bus Access Request to Data Valid
t12
45
ns
Bus Relinquish Time
t13
5
15
ns
Refer to Figure 38 and Figure 39 (Master Serial Interface Modes) 1
CS LOW to SYNC Valid Delay
t14
10
ns
CS LOW to Internal SCLK Valid Delay
t15
10
ns
CS LOW to SDOUT Delay
t16
10
ns
CNVST LOW to SYNC Delay
t17
525
ns
SYNC Asserted to SCLK First Edge Delay2
t18
3
ns
Internal SCLK Period2
t19
25
40
ns
Internal SCLK HIGH2
t20
12
ns
Internal SCLK LOW2
t21
7
ns
SDOUT Valid Setup Time2
t22
4
ns
SDOUT Valid Hold Time2
t23
2
ns
SCLK Last Edge to SYNC Delay2
t24
3
ns
CS HIGH to SYNC HI-Z
t25
10
ns
CS HIGH to Internal SCLK HI-Z
t26
10
ns
CS HIGH to SDOUT HI-Z
t27
10
ns
BUSY HIGH in Master Serial Read after Convert2
t28
See Table 4
CNVST LOW to SYNC Asserted Delay
t29
1.5
μs
SYNC Deasserted to BUSY LOW Delay
t30
25
ns
Refer to Figure 40 and Figure 41 (Slave Serial Interface Modes)
External SCLK Setup Time
t31
5
ns
External SCLK Active Edge to SDOUT Delay
t32
3
18
ns
SDIN Setup Time
t33
5
ns
SDIN Hold Time
t34
5
ns
External SCLK Period
t35
25
ns
External SCLK HIGH
t36
10
ns
External SCLK LOW
t37
10
ns
1In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
2In Serial Master Read during Convert mode. See Table 4 for Serial Master Read after Convert mode.


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