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AD9255BCPZRL7-80 Datasheet(PDF) 39 Page - Analog Devices |
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AD9255BCPZRL7-80 Datasheet(HTML) 39 Page - Analog Devices |
39 / 44 page Data Sheet AD9255 Rev. C | Page 39 of 44 MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Sync Control (Register 0x100) Bits[7:3]—Reserved These bits are reserved. Bit 2—Clock Divider Next Sync Only If the master sync enable bit (Address 0x100, Bit 0) and the clock divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2 allows the clock divider to sync to the first sync pulse it receives and to ignore the rest. The clock divider sync enable bit (Address 0x100, Bit 1) resets after it syncs. Bit 1—Clock Divider Sync Enable Bit 1 gates the sync pulse to the clock divider. The sync signal is enabled when Bit 1 is high and Bit 0 is high. This is continuous sync mode. Bit 0—Master Sync Enable Bit 0 must be high to enable any of the sync functions. If the sync capability is not used, this bit should remain low to conserve power. |
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