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AD9600ABCPZ-105 Datasheet(PDF) 9 Page - Analog Devices |
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AD9600ABCPZ-105 Datasheet(HTML) 9 Page - Analog Devices |
9 / 72 page AD9600 Rev. B | Page 9 of 72 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 4. Parameter Temp AD9600ABCPZ-105/ AD9600BCPZ-105 AD9600ABCPZ-125/ AD9600BCPZ-125 AD9600ABCPZ-150/ AD9600BCPZ-150 Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHz Conversion Rate DCS Enabled Full 20 105 20 125 20 150 MSPS DCS Disabled Full 10 105 10 125 10 150 MSPS CLK Period (tCLK) Full 9.5 8 6.66 ns CLK Pulse Width High Divide-by-1 Mode, DCS Enabled Full 2.85 4.75 6.65 2.4 4 5.6 2.0 3.33 4.66 ns Divide-by-1 Mode, DCS Disabled Full 4.28 4.75 5.23 3.6 4 4.4 3.0 3.33 3.66 ns Divide-by-2 Mode, DCS Enabled Full 1.6 1.6 1.6 ns Divide-by-3 Through Divide- by-8 Modes, DCS Enabled Full 0.8 0.8 0.8 ns DATA OUTPUT PARAMETERS CMOS Mode—DRVDD = 3.3 V Data Propagation Delay (tPD)1 Full 2.2 4.5 6.4 2.2 4.5 6.4 2.2 4.5 6.4 ns DCO Propagation Delay (tDCO) Full 3.8 5.0 6.8 3.8 5.0 6.8 3.8 5.0 6.8 ns Setup Time (tS) Full 5.25 4.5 3.83 ns Hold Time (tH) Full 4.25 3.5 2.83 ns CMOS Mode—DRVDD = 1.8 V Data Propagation Delay (tPD)1 Full 2.4 5.2 6.9 2.4 5.2 6.9 2.4 5.2 6.9 ns DCO Propagation Delay (tDCO) Full 4.0 5.6 7.3 4.0 5.6 7.3 4.0 5.6 7.3 ns Setup Time (tS) Full 5.25 4.5 3.83 ns Hold Time (tH) Full 4.25 3.5 2.83 ns LVDS Mode—DRVDD = 1.8 V Data Propagation Delay (tPD)1 Full 3.0 3.7 4.4 3.0 3.8 4.5 3.0 3.8 4.5 ns DCO Propagation Delay (tDCO) Full 5.2 6.4 7.6 5.0 6.2 7.4 4.8 5.9 7.3 ns CMOS Mode Pipeline Delay (Latency) Full 12 12 12 Cycles LVDS Mode Pipeline Delay (Latency) Channel A/Channel B Full 12/12.5 12/12.5 12/12.5 Cycles Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms Wake-Up Time2 Full 350 350 350 μs OUT-OF-RANGE RECOVERY TIME Full 2 3 3 Cycles 1 Output propagation delay is measured from the CLK+ and CLK− pins 50% transition to the output data pins 50% transition, with 5 pF load. 2 Wake-up time is dependent on the value of the decoupling capacitors. |
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