TLV5638EP

2.7V TO 5.5V LOW POWER DUAL 12BIT DIGITALTOANALOG

CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SGLS130B − JULY 2002 − REVISED DECEMBER 2003

6

POST OFFICE BOX 655303

electrical characteristics over recommended operating conditions (unless otherwise noted)

(continued)

analog output dynamic performance

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ts(FS)

Output settling time, full scale

RL = 10 kΩ,CL = 100 pF,

Fast

1

3

s

ts(FS)

Output settling time, full scale

RL = 10 kΩ,CL = 100 pF,

See Note 11

Slow

3.5

7

µs

ts(CC)

Output settling time, code to code

RL = 10 kΩ,CL = 100 pF,

Fast

0.5

1.5

s

ts(CC)

Output settling time, code to code

RL = 10 kΩ,CL = 100 pF,

See Note 12

Slow

1

2

µs

SR

Slew rate

RL = 10 kΩ,CL = 100 pF,

Fast

12

V/ s

SR

Slew rate

RL = 10 kΩ,CL = 100 pF,

See Note 13

Slow

1.8

V/

µs

Glitch energy

DIN = 0 to 1,

FCLK = 100 kHz,

CS = VDD

5

nV−s

SNR

Signal-to-noise ratio

69

74

S/(N+D)

Signal-to-noise + distortion

fs = 480 kSPS, fout = 1 kHz,

58

67

dB

THD

Total harmonic distortion

fs = 480 kSPS, fout = 1 kHz,

RL = 10 kΩ,CL = 100 pF

−69

−57

dB

Spurious free dynamic range

RL = 10 k ,CL = 100 pF

57

72

NOTES: 12. Settling time is the time for the output signal to remain within

±0.5 LSB of the final measured value for a digital input code change

of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design.

13. Settling time is the time for the output signal to remain within

± 0.5 LSB of the final measured value for a digital input code change

of one count. Not tested, assured by design.

14. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

digital input timing requirements

MIN

NOM

MAX

UNIT

tsu(CS−CK)

Setup time, CS low before first negative SCLK edge

10

ns

tsu(C16-CS)

Setup time, 16th negative SCLK edge (when D0 is sampled) before CS rising edge

10

ns

twH

SCLK pulse width high

25

ns

twL

SCLK pulse width low

25

ns

tsu(D)

Setup time, data ready before SCLK falling edge

10

ns

th(D)

Hold time, data held valid after SCLK falling edge

5

ns