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ADS1605IPAPT Datasheet(PDF) 8 Page - Texas Instruments |
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ADS1605IPAPT Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 38 page  ADS1605 ADS1606 SBAS274H − MARCH 2003 − REVISED MAY 2007 www.ti.com 8 PARAMETER MEASUREMENT INFORMATION DRDY CLK DOUT[15:0] Data N + 1 t 1 t 2 t 2 t 3 t 5 t 6 t 4 t 4 Data N Data N + 2 NOTE: CS and RD tied low. Figure 1. Data Retrieval Timing (ADS1605, ADS1606 with FIFO Disabled) RD, CS DOUT[15:0] t 8 t 7 Figure 2. DOUT Inactive/Active Timing (ADS1605, ADS1606 with FIFO Disabled) TIMING REQUIREMENTS FOR FIGURE 1 AND FIGURE 2 SYMBOL DESCRIPTION MIN TYP MAX UNIT t1 CLK period (1/fCLK) 20 25 1000 ns 1/t1 fCLK 1 40 50 MHz t2 CLK pulse width, high or low 10 ns t3 Rising edge of CLK to DRDY low 10 ns t4 DRDY pulse width high or low 4 t1 ns t5 Falling edge of DRDY to data invalid 10 ns t6 Falling edge of DRDY to data valid 15 ns t7 Rising edge of RD and/or CS inactive (high) to DOUT high impedance 15 ns t8 Falling edge of RD and/or CS active (low) to DOUT active. 15 ns NOTE: DOUT[15:0] and DRDY load = 10pF. |
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