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ADS7817UG4 Datasheet(PDF) 3 Page - Texas Instruments |
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ADS7817UG4 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 21 page ADS7817 3 SBAS066A ELECTRICAL CHARACTERISTICS At –40 °C to +85°C, +V CC = +5V, VREF = +2.5V, fSAMPLE = 200kHz, fCLK = 16 • fSAMPLE, –In = +2.5V, unless otherwise specified. ADS7817 ADS7817B ADS7817C PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS ANALOG INPUT Full-Scale Input Span +In – (–In) –VREF +VREF ✻✻ ✻✻ V Absolute Input Voltage +In –0.3 VCC +0.3 ✻✻ ✻✻ V –In –0.3 4 ✻✻ ✻✻ V Capacitance 15 ✻✻ pF Leakage Current ±1 ✻✻ µA SYSTEM PERFORMANCE Resolution 12 ✻✻ Bits No Missing Codes 11 12 ✻ Bits Integral Linearity Error ±1 ±2 ±0.8 ±2 ±0.5 ±1 LSB(1) Differential Linearity Error ±1 ±2 ±0.7 ±1 ±0.4 ±1 LSB Offset Error ±1 ±6 ✻✻ ✻✻ LSB Gain Error ±0.5 ±4 ✻✻ ✻✻ LSB Noise 63 ✻✻ µVrms Common-Mode Rejection 80 ✻✻ dB Power Supply Rejection 82 ✻✻ dB SAMPLING DYNAMICS Conversion Time 12 ✻✻ Clk Cycles Acquisition Time 1.5 ✻✻ Clk Cycles Throughput Rate 200 ✻✻ kHz DYNAMIC CHARACTERISTICS Total Harmonic Distortion VIN = 5.0Vp-p at 1kHz –83 ✻✻ dB VIN = 5.0Vp-p at 5kHz –81 ✻✻ dB SINAD VIN = 5.0Vp-p at 1kHz 71 ✻✻ dB Spurious Free Dynamic Range VIN = 5.0Vp-p at 1kHz 86 ✻✻ dB REFERENCE INPUT Voltage Range 0.1 2.5 ✻✻ ✻✻ V Resistance CS = VCC 5 ✻✻ G Ω CS = GND, fSAMPLE = 0Hz 5 ✻✻ G Ω Current Drain At Code FF8h 20 100 ✻✻ ✻✻ µA fSAMPLE = 12.5kHz 1.3 20 ✻✻ ✻✻ µA CS = VCC 0.001 3 ✻✻ ✻✻ µA DIGITAL INPUT/OUTPUT Logic Family CMOS ✻✻ Logic Levels: VIH IIH = +5µA3 +VCC +0.3 ✻✻ ✻✻ V VIL IIL = +5µA –0.3 0.8 ✻✻ ✻✻ V VOH IOH = –250µA 3.5 ✻✻ V VOL IOL = 250µA 0.4 ✻✻ V Data Format Binary Two’s Complement ✻✻ POWER SUPPLY REQUIREMENTS VCC Specified Performance 4.75 5.25 ✻✻ ✻✻ V Quiescent Current 460 800 ✻✻ ✻✻ µA fSAMPLE = 12.5kHz(2, 3) 40 ✻✻ µA fSAMPLE = 12.5kHz(3) 330 ✻✻ µA Power Down CS =VCC, fSAMPLE = 0Hz 3 ✻✻ µA TEMPERATURE RANGE Specified Performance –40 +85 ✻✻ ✻✻ °C ✻ Specifications same as ADS7817. NOTE: (1) LSB means Least Significant Bit, with VREF equal to +2.5V, one LSB is 1.22mV. (2) fCLK = 3.2MHz, CS = VCC for 241 clock cycles out of every 256. (3) See the Power Dissipation section for more information regarding lower sample rates. |
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