TIMING REQUIREMENTS

TLV5608

TLV5610

TLV5629

ELECTRICAL CHARACTERISTICS (continued)

over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG OUTPUT DYNAMIC PERFORMANCE

Fast

1

3

Output settling time (full scale)

(4)

µs

Slow

3

7

Fast

0.5

1

Output settling time, code to

(5)

µs

code

Slow

1

2

Fast

4

10

SR

Slew rate

(6)

V/

µs

Slow

1

3

Glitch energy

4

nV-s

Channel crosstalk

-90

dB

(4)

Settling time is the time for the output signal to remain within +0.5 LSB of the final measured value for a digital input code change of

0x80 to 0xFFF and 0xFFF to 0x080, respectively. Assured by design; not tested.

(5)

Settling time is the time for the output signal to remain within +0.5 LSB of the final measured value for a digital input code change of one

count. The max time applies to code changes near zero scale or full scale. Assured by design; not tested.

(6)

Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full scale voltage.

(7)

Code transition: TLV5610 - 0x7FF to 0x800, TLV5608 - 0x7FC to 0x800, TLV5629 - 0x7F0 to 0x800

DIGITAL INPUTS

MIN

NOM

MAX

UNIT

Setup time, FS low before next negative SCLK edge

8

ns

10

ns

rising edge of FS.

µC mode only

10

ns

DSP mode, setup time, SLCK low before FS low.

5

ns

LDAC duration low

10

ns

SCLK pulse duration high

16

ns

SCLK pulse duration low

16

ns

Setup time, data ready before SCLK falling edge

8

ns

Hold time, data held valid after SCLK falling edge

5

ns

FS duration high

10

ns

FS duration low

10

ns

See AC

Settling time

specs

Copyright © 2000–2008, Texas Instruments Incorporated

Submit Documentation Feedback

5

Product Folder Link(s): TLV5608 TLV5610 TLV5629