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TMS320C6748BZWT3 Datasheet(PDF) 2 Page - Texas Instruments |
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TMS320C6748BZWT3 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 273 page TMS320C6748 SPRS590E – JUNE 2009 – REVISED AUGUST 2013 www.ti.com • Two Master/Slave Inter-Integrated Circuits Capture Channels (I2C Bus™) – Two 8-Bit SD (BT.656), Single 16-Bit Video • One Host Port Interface (HPI) with 16-Bit-Wide Display Channels Muxed Address and Data Bus For High • Universal Parallel Port (uPP): Bandwidth – High-Speed Parallel Interface to FPGAs and • Programmable Real-Time Unit Subsystem Data Converters (PRUSS) – Data Width on Both Channels is 8- to 16-Bit – Two Independent Programmable Real-Time Inclusive Unit (PRU) Cores – Single-Data Rate or Dual Data Rate Transfers • 32-Bit Load-Store RISC Architecture – Supports Multiple Interfaces with START, • 4KB of Instruction RAM Per Core ENABLE, and WAIT Controls • 512 Bytes Data RAM Per Core • Serial ATA (SATA) Controller: • PRUSS can be Disabled via Software to – Supports SATA I (1.5 Gbps) and SATA II Save Power (3.0 Gbps) • Register 30 of Each PRU is Exported – Supports All SATA Power Management From the Subsystem in Addition to the Features Normal R31 Output of the PRU Cores – Hardware-Assisted Native Command – Standard Power Management Mechanism Queueing (NCQ) for up to 32 Entries • Clock Gating – Supports Port Multiplier and Command- • Entire Subsystem Under a Single PSC Based Switching Clock Gating Domain • Real-Time Clock (RTC) with 32-kHz Oscillator – Dedicated Interrupt Controller and Separate Power Rail – Dedicated Switched Central Resource • Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers) • USB 1.1 OHCI (Host) with Integrated PHY (USB1) • One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General- • USB 2.0 OTG Port with Integrated PHY (USB0) Purpose Timers) – USB 2.0 High- and Full-Speed Client • Two Enhanced High-Resolution Pulse Width – USB 2.0 High-, Full-, and Low-Speed Host Modulators (eHRPWMs): – End Point 0 (Control) – Dedicated 16-Bit Time-Base Counter with – End Points 1,2,3,4 (Control, Bulk, Interrupt, Period And Frequency Control or ISOC) RX and TX – 6 Single-Edge Outputs, 6 Dual-Edge • One Multichannel Audio Serial Port: Symmetric Outputs, or 3 Dual-Edge – Two Clock Zones and 16 Serial Data Pins Asymmetric Outputs – Supports TDM, I2S, and Similar Formats – Dead-Band Generation – DIT-Capable – PWM Chopping by High-Frequency Carrier – FIFO Buffers for Transmit and Receive – Trip Zone Input • Two Multichannel Buffered Serial Ports: • Three 32-Bit Enhanced Capture Modules – Supports TDM, I2S, and Similar Formats (eCAPs): – AC97 Audio Codec Interface – Configurable as 3 Capture Inputs or 3 – Telecom Interfaces (ST-Bus, H100) Auxiliary Pulse Width Modulator (APWM) Outputs – 128-Channel TDM – Single-Shot Capture of up to Four Event – FIFO Buffers for Transmit and Receive Time-Stamps • 10/100 Mbps Ethernet MAC (EMAC): • Packages: – IEEE 802.3 Compliant – 361-Ball Pb-Free Plastic Ball Grid Array – MII Media Independent Interface (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch – RMII Reduced Media Independent Interface – 361-Ball Pb-Free PBGA [ZWT Suffix], – Management Data I/O (MDIO) Module 0.80-mm Ball Pitch • Video Port Interface (VPIF): • Commercial, Extended, or Industrial – Two 8-Bit SD (BT.656), Single 16-Bit or Temperature Single Raw (8-, 10-, and 12-Bit) Video 2 TMS320C6748 Fixed- and Floating-Point DSP Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C6748 |
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