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TMS320C6748BZWTD4E Datasheet(PDF) 3 Page - Texas Instruments

Part # TMS320C6748BZWTD4E
Description  TMS320C6748 Fixed- and Floating-Point DSP
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TMS320C6748BZWTD4E Datasheet(HTML) 3 Page - Texas Instruments

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TMS320C6748
www.ti.com
SPRS590E – JUNE 2009 – REVISED AUGUST 2013
1.2
Applications
Currency Inspection
Machine Vision (Low-End)
Biometric Identification
1.3
Description
The device is a low-power applications processor based on a C674x DSP core. This device provides
significantly lower power than other members of the TMS320C6000™ platform of DSPs.
The device enables OEMs and ODMs to quickly bring to market devices with the following features
through the maximum flexibility of a fully integrated, mixed processor solution:
Robust operating systems
Rich user interfaces
High processor performance
The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a 32-
KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache. The
level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and
data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.
Although the DSP L2 is accessible by other hosts in the system, an additional 128KB of RAM shared
memory is available for use by other hosts without affecting DSP performance.
For security-enabled devices, TI’s Basic Secure Boot lets users protect proprietary intellectual property
and prevents external entities from modifying user-developed algorithms. By starting from a hardware-
based “root-of-trust”, the secure boot flow ensures a known good starting point for code execution. By
default, the JTAG port is locked down to prevent emulation and debug attacks; however, it can be enabled
during the secure boot process during application development. The boot modules are encrypted while
sitting in external nonvolatile memory, such as flash or EEPROM, and are decrypted and authenticated
when loaded during secure boot. This protects customers’ IP and lets them securely set up the system
and begin device operation with known, trusted code.
Basic Secure Boot uses either SHA-1 or SHA-256, and AES-128 for boot image validation. Basic Secure
Boot also uses AES-128 for boot image encryption. The secure boot flow employs a multilayer encryption
scheme which not only protects the boot process but offers the ability to securely upgrade boot and
application software code. A 128-bit device-specific cipher key, known only to the device and generated
using a NIST-800-22 certified random number generator, is used to protect customer encryption keys.
When an update is needed, the customer uses the encryption keys to create a new encrypted image.
Then the device can acquire the image through an external interface, such as Ethernet, and overwrite the
existing code. For more details on the supported security features or TI’s Basic Secure Boot, refer to the
TMS320C674x/OMAP-L1x Processor Security User’s Guide (SPRUGQ9).
The peripheral set includes:
A 10/100 Mb/s Ethernet media access controller (EMAC) with a management data input/output (MDIO)
module
One USB2.0 OTG interface
One USB1.1 OHCI interface
Two I2C Bus interfaces
One multichannel audio serial port (McASP) with 16 serializers and FIFO buffers
Two multichannel buffered serial ports (McBSPs) with FIFO buffers
Two SPI interfaces with multiple chip selects
Four 64-bit general-purpose timers each configurable (one configurable as a watchdog)
A configurable 16-bit HPI
Up to 9 banks of 16 pins of general-purpose I/O (GPIO) with programmable interrupt and event
generation modes, multiplexed with other peripherals
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6748 Fixed- and Floating-Point DSP
3
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